Design Automation Conference 2023

By extending the instruction set, a processor can tackle an application more efficiently.

The test and analysis GUI from OPENEDGES, code-named PHY Vision, serves as a comprehensive cockpit for visualizing and optimizing the performance of the DDR PHY.

The ASIC design service and IP provider displays a comprehensive array of offerings for a multitude of applications.

The company's JSPICE software, used for 25 years in-house to make its own PLL and DLL IP, is now available through a beta test in advance of a commercial release.

The Versal Premium FPGA targets EDA simulation and verification applications.