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Contemplating Custom Instructions for RISC-V

July 7, 2023
By extending the instruction set, a processor can tackle an application more efficiently.

This article is part of our DAC 2023 coverage.

Most computer instruction sets include unutilized instructions that typically generate a fault or act as a no-op instruction. Sometimes this is by design, especially for architectures that are intended to be extended, such as RISC-V.

Thus, a chip designer can add instructions that will enhance the software developer’s repertoire. It allows an application to take advantage of these instructions that may perform special functions or operate more efficiently than what’s provided by default.

Custom instructions require additional logic to implement the desired functionality as well as enhancements to the compiler so that software can utilize them. The chip design cycle to address the inclusion of custom instructions is a relatively straightforward process (see figure).

If you have a chance to attend this year’s Design Automation Conference, you may want to attend the session “Extending RISC-V with Custom Instructions.” It’s presented by Imperas Software’s Jon Taylor.

In case you can’t make the session, Jon gave a similar talk earlier this year. You can download the presentation for some insights into the design process.

For more DAC 2023 coverage, visit our digital magazine.