This third part in our low-noise synthesizer design series is the medium-length online version. In print are the abridged versions, while full-length versions are available at www.longwingtech.com. Part 1 (Dec. 2018) covered basic design for functionality and stability. Part 2 (Feb. 2019) covered the many noise sources in the synthesizer outside of the actual synthesizer IC. This third article looks into synthesizer IC noise, the closed-loop shaping of noises, and related issues such as optimum bandwidth.
Here, a key metric for characterizing synthesizer IC noise is developed. This material also leads directly to analysis of optimum loop bandwidth, taking all noise sources into account—a key design topic that to the author’s knowledge is not published elsewhere. For reasons of space, some important parts of this subject are deferred to the full version on the Longwing website. The long-version material includes derivation of charge-pump noise in current form, spur noise, SPICE modeling of PLL noise, and application noise requirements. Part 4 will review parts and tools available to the low-noise synthesizer designer. The concluding Part 5 will present low-noise design examples.