Electronic Products (EPI) recently announced advanced capabilities to produce hi-rel transistor-outline, or TO, packages and headers. Originally developed by the semiconductor and microelectronics industry in the 1950s, the TO design for packages and headers was created to support the early development of hermetic devices in a common suite of easy-to-implement package outlines.
While there are plastic versions of TO packages, EPI’s focus has been to improve on standardized TO packages and headers made of metals. The goal is that these will help meet the most rigorous hermetic standards and screening requirements of today’s hi-rel semiconductor devices and components.
The basic TO or “metal can” package consists of a metal base with leads exiting through a glass seal. The glass-sealing process is among the many areas in which EPI has made innovations, specifically in both compression-seal and matched-seal technology. EPI’s matched seals typically use coefficient of thermal expansion (CTE) matched ASTM-F15 alloy (Kovar) and CTE matched glass compositions.
The company’s highest-performing compression seals employ plain carbon steel 1010 and ASTM-F30 (Alloy 52) with higher CTE to compress the glass upon cooling during the fusing process of the TO package or header. After device assembly in the package, the customer applies a metal lid that’s resistance-welded with precision to the metal base to form a superior hermetic seal.
The TO design was developed to support the initiative in 1944 put forth by the Joint Electron Device Engineering Council (JEDEC). JEDEC initially functioned within the engineering department of the Electronic Industries Association (EIA); its primary activity was to develop and assign part numbers to devices. Over the next 50 years, JEDEC’s work expanded into developing test methods and product standards that proved vital to the development of the semiconductor industry. In addition to several standardized TO package outlines and header designs, other landmark standards initiated by JEDEC committees include:
- The electrostatic discharge (ESD) symbol used worldwide on semiconductor devices.
- Specifications for computer memory, ranging from dynamic RAM chips and memory modules to double-data-rate (DDR) synchronous DRAM and flash components.
- Development and publication of a manual of common terms and definitions for the semiconductor industry.
- Standards, publications, and educational events addressing the migration to lead-free manufacturing processes. One of the most popular standards in JEDEC history—J-STD-020—resulted from this work.
TO packages and headers are in use today in all areas of microelectronic applications, on both the transmit and receive side of a transceiver system. They’re also proven in high-speed data transfer, infrared, and other optoelectronic applications. EPI’s TO packages and headers are qualified to the rigorous JESD9C standard that’s used in conjunction with the most up-to-date test methods described by MIL-STD 883.
Microelectromechanical systems (MEMS) packaging represent a new area of microelectronic packaging applications for the TO package. EPI is currently developing advanced solutions for this packaging option. MEMS systems, which now enable optical signals to be switched using a range of small mobile mirrors, are becoming increasingly accepted in high-volume applications like LCD projectors.
EPI specializes in the design and manufacture of both legacy and custom-engineered TO packages and headers used in a variety of high-performance applications, such as RF/microwave/wireless, optoelectronics, photonics, and power-semiconductor applications. In addition to traditional “TO-cans,” optional styles include stamped, coined, cold-headed, drawn, machined, multi-pin headers, and more.
To learn more, visit: https://www.elecprodinc.com/to-packages-and-header.