Analog Devices Debuts a Wideband, Direct-RF Digitizing Development Platform

July 5, 2022
ADI's Nikhil Ahuja shows off the company's AD9213 12-bit, 10-Gs/s data converters coupled with its ADF4377 PLL VCOs to create a scalable clocking architecture.

This article is part of our IMS 2022 coverage.

MWRF: Hi, it’s David Maliniak again at IMS2022. I’m with Nikhil at the Analog Devices booth. He’s going to give us a demo of Analog Devices’ latest wideband, direct-RF digitizing development platform.

Nikhil Ahuja: As customers start working toward looking at sampling at higher bandwidth, and also wanting higher sample rates and wanting wider bandwidths, we are making sure we have all the components available to try and build such a system, all while supplying the linearity and the software that would be required.

So what we have here is our 20-Gsample RF system, which uses two of our AD9213s, which are 12-bit, 10-Gs/s, state-of-the-art-data converters. The data converters are synchronized within one sample of each other. They’re also supplied by the ADF4377, which is our latest, state-of-the-art PLL VCO. The two PLL VCOs can also be synchronized. As a result of that, what we can do is use two of our 10-Gs/s data converters to get a 20-Gs/s data converter.

The way we do it is we would use one of the ADF4377s and invert the clock by 180° in phase. That results in every other sample coming from a different data converter. The way we implement it is that we have this clocking architecture that is scalable, and one of the central components of it that allows us to do interleaving is the ADF4377. There’s a reference clock that comes in, that gets split to the 4377s to make sure both of them are synced. Then, the 4377s are providing the sample clock to the 9213s, and one of those sample clocks is inverted by 180°, and that’s what enables us to do interleaving.

One of the advantages of having a clocking architecture like this is that it can be scaled down. So, each of these boards requires only a single reference. So, essentially, what you can do is use another one of our clocking chips as a clock references, and provide it to as many boards as you like. So, with each of these that are 20-Gs/s data converters, you could potentially build an array and everything would be synchronized and they can… the clocking architecture that we have.

MWRF: Tell us a little more about the ADF4377 itself.

Nikhil Ahuja: The ADF4377 is our lowest phase noise, very low jitter, less than 27 fsRMS, PLL VCO. It’s generated as a combination of all the leadership technology we have now in clocking, power, and timing. It’s perfectly suited for building such systems where you want to go from just one data converter to multiples and fan out.

This article is part of our IMS 2022 coverage.