In multiband, multi-mode RF transceivers, engineers often opt to use a single, wideband phase-locked-loop (PLL) synthesizer. Before the PLL's closed-loop locking process begins, voltage-controlled-oscillator (VCO) frequency calibration is used to find the closest sub-band turning curve to a target frequency. A method that is suitable for ?S fractional-N synthesizers is now being reported by Jaewook Shin from the University of California in Los Angeles and Hyunchol Shin from Seoul's Kwangwoon University.
Typically, a PLL synthesizer's wide tuning range is realized by employing an LC-tuned VCO with a switched capacitor bank. This approach suffers drawbacks, howeverparticularly when the required tuning range grows wider. Many therefore opt for the fast and accurate auto-calibration of the VCO frequency and loop bandwidth. The approach presented in this project is mainly based on a high-speed frequency-to-digital converter (FDC), which detects the VCO frequency on chip. That information is then used to calibrate the VCO frequency and loop bandwidth.
Essentially, the loop-bandwidth calibration circuit measures the VCO gain. It then uses it to control the charge-pump current. For the VCO frequency calibration, a minimum error-code finding block improves the calibration accuracy by finding the code that is closest to the target frequency.
The researchers implemented a 1.9-to-3.8-GHz ?S fractional-N synthesizer in 0.13-m CMOS. In doing so, they were able to demonstrate that the loop-bandwidth calibration is completed in 1.1 to 6.0 s with 2% accuracy. See "A 1.9-3.8 GHz ?S Fractional-N PLL Frequency Synthesizer with Fast Auto-Calibration of Loop Bandwidth and VCO Frequency," IEEE Journal Of Solid-State Circuits, March 2012.