16-b ADCs Flaunt 86-dB Dynamic Range To 10 MHz

Jan. 26, 2009
A PERFORMANCE GAP HAS EXISTED between pipeline and SAR analog-to-digital-converter (ADC) architectures because no converters could satisfy emerging applications that simultaneously demand high dynamic range, wide bandwidth, and low power. Now, ...

A PERFORMANCE GAP HAS EXISTED between pipeline and SAR analog-to-digital-converter (ADC) architectures because no converters could satisfy emerging applications that simultaneously demand high dynamic range, wide bandwidth, and low power. Now, the 16-b AD9261 single-channel and AD9262 dual-channel continuous-time sigma-delta (CTSD) converter ADCs and AD9267 CTSD modulator couple low noise and 86-dB dynamic range with a bandwidth to 10 MHz. The AD9261 and AD9262 feature an on-chip phase-locked-loop (PLL) clock multiplier, decimation filters, and sample-rate converters. They can operate at data rates from 30 and 160 MSamples/s and feature spurious-free dynamic range (SFDR) of 87 dBc. The dual-channel AD9267, which features only the 640-MSample/s modulator core and PLL clock multiplier, presents the high-speed data directly to the output. The 150- to 350-mW-per-channel power consumption of the new CTSD converters is matched to a range of communications and industrial applications, such as direct downconversion. P&A: $30 for the AD9262, $37 for the AD9262-5, and $48 for the AD9262-10 in quantities of 1000; will be available in volume in April.

Analog Devices, Inc., 3 Technology Way, Norwood, MA 02062; (781) 329-4700, Internet: www.analog.com.

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