Margin Test Solution Simplifies and Speeds PCIe Gen 3 and Gen 4 Analysis

Oct. 31, 2022
The new TMT4 Margin Tester challenges the conventions of PCIe testing, offering fast test times, plug-and-play setup, and easy-to-use interface.

This video appeared in Electronic Design and has been published here with permission.

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A solution released by Tektronix promises to change PCI Express testing, accelerating time-to-market, reducing cost, and increasing accessibility. The new TMT4 Margin Tester challenges the conventions of PCIe testing, offering fast test times, plug-and-play setup, and an easy-to-use interface.

A specialized testing tool for design and validation of PCIe Gen 3 and Gen 4 motherboards, add-in cards, and system designs, the TMT4 Margin Tester enables engineers at all levels of experience to evaluate the health of transmitter (Tx) and receiver (Rx) links faster than ever. The platform supports the majority of common PCIe form factors, including CEM, M.2, U.2, and U.3, with testing capabilities of up to 16 lanes across PCIe presets 0-9, using a single standard connector.

The Tektronix TMT4 Margin Tester is presented as a great option to conduct earlier and more frequent evaluation of board- or system-level link health during design and validation. Intended to complement full validation and compliance testing systems consisting of oscilloscopes and BERTs, the TMT4 tester makes it possible to uncover issues earlier in the design process prior to an in-depth examination using traditional equipment.

The new tester enables engineers at all levels of expertise to test PCIe devices across up to 160 combinations of lanes and presets in as little as 20 minutes at Gen 4 speeds. Multi-lane testing capabilities enable users to significantly improve overall speed by reducing the number of connection changes needed to perform testing.

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