How to Achieve Ultra-Fast Power-Supply Transient Response in RF Apps

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What you’ll learn:

• Why fast power-supply load transient response is critical in RFSoC circuits.
• How to use pre-charge signals to drive regulators.
• Using active drooping circuits to minimize power-supply recovery time.

Signal processing units and system-on-chip (SoC) units usually possess abruptly changingload-transientprofiles.Thisloadtransientwillresultinadisturbanceonthesupplyvoltagethat’scriticalinRFapplications,astheclockfrequency will be highly affected by the varying supply voltage. Thus, RFSoCsusuallyapplyblankingtimeduringtheloadtransient.

In 5G applications, information qualityishighlyrelatedtothisblankingperiodduringthetransition.As a result,there’sanincreasingneedtominimizetheload-transienteffectonthepower-supplysidetoimprovethesystem-levelperformanceforanyRFSoCsystem.Thisarticlewillintroduce several methods used in RF applications to achieve fast transient response in apower-supplydesign.

FastTransientSwitching Regulators

One of the most straightforward methods to achieve fast transient power railsistoselectregulatorsthatfeaturefasttransientperformance. An example of such devices is ADI’s SilentSwitcher3family of ICs, which offer exceptionally low-frequency output noise, fast transientresponse, low-EMI emissions, and high efficiency.

The regulators feature an ultra-high-performance error-amplifier design that can provide extra stabilization even with an aggressive compensation. Their 4-MHz maximum switching frequency enablestheICstopushthecontrol-loopbandwidthtothemid-hundred-kilohertzrangeinafixed-frequency,peak-currentcontrolmode. The table lists theSilentSwitcher3ICsthatdesignerscanselect to achieve fast transient performance.

Figure1 showsatypicalpowersupply with a 1-VoutputbasedontheLT8625SPfora5GRFSoC, which needs fast transient response and low ripple/noise level at the sametime.The1-Vloadconsistsofbothtransmit/receive-relatedcircuitsaswellaslocaloscillators (LOs) and voltage-controlled oscillators (VCOs).

The transmit/receive loads see abrupt load-current change during frequency-division duplex(FDD)operation.Atthesametime,LOs/VCOssee a constantloadbutrequirecriticalhigh accuracy and low noise.

The high-bandwidth feature of the LT8625SP enables designerstopowerthetwocritical1-VloadgroupsfromasingleICbyseparatingthe dynamic load and static load with a second inductor (L2). Figure 2 shows theoutput-voltage response with a dynamic load transient of 4 to 6 A. The dynamicload recovers within 5 µs with less than 0.8% peak-to-peak voltage, whichminimizes the effect on the static load side with a less than 0.1% peak-to-peakvoltage.

Thiscircuitcanbemodifiedtoaccommodateotheroutputcombinations,like 0.8 V and 1.8 V, that can all directly supply the RFSoC load without the LDOregulator stage due to the ultra-low noise in the low-frequency range, low voltageripple, and ultrafast transient response.

In time-division-duplex (TDD) mode, the noise-critical LOs/VCOs become loadedand unloaded together with the transmit/receive mode changes. Thus, a simplified circuit (Fig. 3) can be used, because all of the loads are dynamic in character while more critical post-filtering is required to maintain thelow-ripple/low-noise feature for the LOs/VCOs.

Using a three-terminal capacitor in feedthrough mode achieves enough post-filtering with a minimizedequivalent L that maintains a fast bandwidth for the load transients. The feedthrough capacitor, together with the remote-side output capacitors, forms two moreLCfilterstages.All of theinductancescomefrom the equivalent series inductances (ESLs)ofthethree-terminalcapacitor, whichisverysmallandlessharmfultotheloadtransient.

Figure3 alsoillustrates aneasyremote-sensingconnectionfortheSilentSwitcher3family. Duetothe unique reference generation and feedback technology, one only needs to Kelvin-connect the SET pin capacitor’s (C1) ground and the OUTS pin to the desiredremote feedback point. No level-shifting circuits are needed for this connection. Figure 4 shows a 1-A load transient-response waveform with <5-μs recovery timeand <1-mV output-voltage ripple.

Pre-chargeSignalsDrive Regulators

Insomecases,thesignal-processingunitispowerfulwithenough general-purpose I/Os (GPIOs),and because the transient event is predictable, thesignal processing is well scheduled. This usually happens in some FPGA power-supply designs where thepre-charge signal can be generated to help power the supply transient response.

Figure5 showsatypicalapplicationcircuitusingthepre-chargesignalgenerated by the FPGA to provide a bias before the real load transition occurs. As a result, the LT8625SPcanhaveextratimetoaccommodatetheloaddisturbancewithouttoo largeofaV_OUTdeviationandrecoverytime.Thetuningcircuitfrom the FPGA’sGPIOtotheinputoftheinverterhasbeenomittedsincethepre-chargesignalisactingasa disturbance on the feedback. The level is controlled at 35 mV.

Moreover, toavoidthepre-chargesignaleffectonthesteadystate,ahigh-passfilterisimplementedbetweenthepre-chargesignalandtheOUTS pin.Figure6showsaload transient-response waveform of 1.7to 4.2 A. The pre-charge signal is applied to thefeedback(OUTS pin)aheadoftherealloadtransient, achieving a recovery time of less than5µs.

ActiveDroopingonCircuitforUltra-Fast Recovery Transient

In beamformer applications, the supply voltage changes constantly to accommodatedifferentpowerlevels.Asaresult,theaccuracyrequirementforthesupply voltage is usually 5% to 10%.

In this application, stability is moreimportantthanthevoltageaccuracy, becauseaminimizedrecoverytimeduringtheloadtransientwillmaximizethedata-processingefficiency.Adroopingcircuitis well-suited for thisapplication becausethedroopingvoltagewillreduceoreven eliminate the recovery time.

Figure 7 shows the schematicfor an active drooping circuit for the LT8627SP. An extra drooping resistor hasbeen added between the error amplifier’s negative input (OUTS) and the output(VC) to maintain a steady-state error in the feedback control loop during thetransient.

The drooping voltage can be expressed as:

Whereas∆V_OUTistheinitialvoltagevariationcausedbytheloadtransient, ∆I_OUTistheloadtransientcurrent,andgistheVCpin-to-switchcurrentgain. When designing the drooping circuit shown in Figure 7, one should be aware of a couple of special considerations:

• The drooping current should not exceed the VC pin current limit. For the LT8627SP’s error amplifier output, limit the current to below 200 µA to avoid saturation; this can be achieved by changing R7 and R8 values.
• The drooping voltage needs to accommodate the output capacitance so that the voltage deviation during the transient is on a similar level of the drooping voltage to achieve minimum recovery time during the transient.

Figure8 showstypicalwaveformsfortheabove-mentionedcircuitduringaloadtransient from 1 A to 16 A and back to 1 A.Notethatthe16-A-to-1-Aload-transientspeedisnolongerbottleneckedbythebandwidth,but rather bytheminimumontimeof theregulator.

Conclusion

The wireless RF field is becoming increasingly dependent on calculations and sensitive to the transient-response time due to the time-criticalnatureofthehigh-speed signal processing. System design engineers face challenges to increase the power-supplytransient-responsespeedto minimizetheblankingtime. Basedontheload conditions, special techniques and circuits can be applied tofurther improve the transient response.