Time-Interleaved ADC Benefits 60-GHz Transceiver

Oct. 8, 2012
For integration into a 60-GHz wireless transceiver for gigabit applications, this ADC implements a time splitting subranging architecture to boost speed.

A number of standards have sprung up in the 57-to-64-GHz band, such as IEEE 802.15.3c, IEEE 802.11ad, and WirelessHD. No matter the standard, they all have one common goal: to speed the realization of integrated circuits (ICs) that can support large wireless data transfers at those millimeter-wave frequencies. Due to these ICs’ wide applicable bandwidth and modest circuit-implementation complexity, low-order data modulation approaches like binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK) are often chosen. To provide power-efficient, low-cost system-on-a-chip (SoC) solutions for such applications, medium-resolution (6 to 8 b), CMOS analog-to-digital converters (ADCs) with speeds beyond 1 GSamples/s are needed. At the University of California, a 7-b, 2.2-GSamples/s, time-interleaved subranging CMOS ADC has been presented for low-power gigabit-wireless-communications SoCs by I-Ning Ku, Zhiwei Xu, Yen-Cheng Kuan, Yen-Hsiang Wang, and Mau-Chung Frank Chang.

Of course, a single ADC running beyond gigahertz rates is feasible in the advanced CMOS nodes. Yet a time-interleaved ADC is preferred because it can achieve better power efficiency. The time-interleaved ADC combines multiple sub-ADCs—which operate at a lower sampling rate—to deliver the required high sampling rate. Unfortunately, the time-interleaved architecture suffers from channel mismatches in timing, offset, and gain among individual sub-ADCs. Because the total area increases as the number of channels rises, the associated routing of multiple-phase clock signals and digital outputs also becomes complicated. In addition, excessive parasitic capacitance is introduced by the long routing wires of the clocks and outputs.

To achieve high power efficiency and performance, a time-interleaved ADC design thus requires the proper sub-ADC architecture and a strategy for alleviating channel mismatches. To boost the speed of individual ADC channels, for example, this team invented a time-splitting subranging architecture. It raises the speed of individual ADC channels while reducing the total number of interleaved channels to four. In addition, the researchers proposed a low-power and fast-settling distributed resistor array for reference voltages to mitigate gain mismatches within channels. The channel offset mismatches are calibrated through the digital-controlled corrective current sources, which are embedded in the track-and-hold (T/H) amplifiers of each sub-ADC. 

Ultimately, the team created a prototype in 65-nm CMOS that occupies only 0.3 mm2 of chip area. It consumes 40 mW at 2.2 GSamples/s from a 1-V supply. The ADC boasts measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 38 and 46 dB, respectively, with a 1.08-GHz input at the 2.2 GSamples/s sampling rate. The effective number of bits (ENOB) is 6.0 b at Nyquist rate while the figure of merit (FOM) is 0.28 pJ/conv.-step. The researchers were able to integrate the ADC into a self-healing wireless-transceiver SoC. See “A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications,” IEEE Journal Of Solid State Circuits, Aug. 2012, p. 1854.

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