Integrated 60-GHz Transceiver Conquers Four-Channel Communications

Integrated 60-GHz Transceiver Conquers Four-Channel Communications

This 60 GHz, 16QAM transceiver includes the RF front end, antenna, and analog and digital baseband circuitry to achieve four-channel wireless communication for QPSK and 16QAM with low power consumption.

Many of today’s backhaul wireless-communications standards use a 60-GHz carrier frequency. Because that frequency is 25 times higher than that of a conventional wireless local-area network (WLAN), the demands on the RF front-end design are quite stringent. Compared to conventional transceivers, a 60-GHz transceiver in particular poses many design challenges. To overcome these issues, a 60-GHz, direct-conversion RF front end and baseband transceiver has been created that incorporates analog and digital circuitry for the physical-layer (PHY) functions. The entire system—including RF and baseband circuitry using a 6-dBi antenna built in an organic package—can transmit 3.1 Gb/s over 1.8 m in quadrature phase shift keying (QPSK) and 6.3 Gb/s over 0.05 m in 16-state quadrature amplitude modulation (16QAM).

This 65-nm CMOS front end consumes 31 mW in transmitting mode and 223 mW in receiving mode. It can handle 16QAM wireless communication beyond 7 Gb/s for every channel of the 60-GHz standards. Impressively, that performance feature can be extended to 10 Gb/s. The transceiver’s 40-nm CMOS baseband circuitry, which includes analog, digital, and input/output (I/O) circuitry, consumes 196 and 427 mW, respectively, for 16QAM in transmit and receive modes. In the analog baseband portion, in particular, a 5-b, 2304-MSample/s analog-to-digital converter (ADC) consumes 12 mW while a 6-b, 3456-MSample/s digital-to-analog converter (DAC) consumes 11 mW. For its part, the digital baseband circuitry—while integrating all PHY functions—boasts a power-conserving (1440, 1344), low-density parity-check (LDPC) decoder that consumes 74 mW with a user bit rate of 6.3 Gb/s and energy efficiency of 11.8 pJ/b.

This transceiver is the brainchild of an impressive team: Kenichi Okada, Masaya Miyahara, Hiroki Asada, Ryo Minami, Ahmed Musa, Yuuki Tsukui, Hironori Sakaguchi, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, and Akira Matsuzawa from the Tokyo Institute of Technology; Toyota’s Keitarou Kondou, Masashi Shinagawa, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Makoto Noda, and Tatsuya Yamaguchi; Takahiro Sato from Nintendo Corp.; Naoki Shimasaki and Rui Murakami from Panasonic Corp.; and Toshihiko Ito from ABB. See “Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver with Low-Power Analog and Digital Baseband Circuitry,” IEEE Journal Of Solid-State Circuits, Jan. 2013, p. 46.

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