Clocking Family Trims Noise In Wireless Infrastructure

A family of three ultra-low-noise clock buffers, dividers, and distributors vows to simplify system clock design while providing additive noise of just 30 fs of additive root-mean-square (RMS) jitter.

The LMK01000, LMK01010, and LMK01020, which hail from National Semiconductor (www.national.com) divide and distribute low-jitter clocks throughout high-performance systems like wireless infrastructures and medical ultrasound and imaging. The family comes in three output configurations. The LMK01000 has a mix of three low-voltage differential signaling (LVDS) and five low-voltage positive-emitter-coupled logic (LVPECL) outputs. The LMK01010 is offered with eight LVDS outputs to address low-power applications while the LMK01020 has eight LVPECL outputs to support ultra-high-performance applications.

POWER PERSPECTIVE
From a power perspective, these products provide power-noise specifications that place them among National's PowerWise family of energy-efficient products. The LMK01000 offers 8.9 mW-ps per channel while the LMK01010 is rated at 5.3 mW ps per channel and the LMK01020 at 11.2 mW ps per channel. The devices' low additive jitter allows system designers to distribute multiple copies of a clean clock while maintaining clock integrity. It also eliminates the need for additional jitter cleaning components. Each device's output offers a programmable skew control circuit that simplifies board layout, enabling the designer to adjust the skew of each clock output and compensate for board trace mismatch.

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