60-GHz Receiver May Be Realized In CMOS

Wireless communications systems like highspeed personal-area networks and real-time video transmission demand performance that is above the Gigabit-per-second range. As a result, such systems may require the bandwidth provided by a 60-GHz millimeter-wave transceiver. The traditional approach behind such a transceiver is to leverage compoundsemiconductor monolithic microwave integrated circuits (MMICs). Yet, that 60-GHz transceiver may potentially be realized in silicon-process ICs like silicon-germanium (SiGe) BiCMOS and CMOS. Such processes are much lower in cost than compound-semiconductor process ICs. Because the silicon process' yield is much higher, a highly integrated transceiver can be achieved as well. A 60-GHz receiver front-end chip fabricated in 90-nm CMOS has been presented by Toshiba Corp.'s (www.toshiba.com) Toshiya Mitomo, Ryuichi Fujimoto, Naoko Ono, Ryoichi Tachibana, Hiroaki Hoshino, Yoshiaki Yoshihara, Yukako Tsutsumi, and Ichiro Seto.

At 61.5 GHz, the receiver chip delivered measured power gain of 22 dB and a noise figure of 8.4 dB. The chip consists of a lownoise amplifier (LNA), downconversion mixer, and phase-locked-loop (PLL) synthesizer. It can generate the local-oscillator (LO) signal from the phase-locked synthesizer. The chip receives radio signals with an on-chip dipole antenna.

To realize a CMOS 60-GHz receiver RF front end, the chip used a fully differential, receiver front end and a downconversion mixer operating with low LO amplitude. The RF front-end IC can be applied for a BPSK demodulator by using synchronized detection. See "A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer," IEEE Journal of Solid- State Circuits, April 2008, p. 1030.

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