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Power Supply Rejection Ratio (PSRR) in RF Circuit Designs

Power Supply Rejection Ratio (PSRR) in RF Circuit Designs

Is it Power Supply Rejection Ratio, Power Supply Ripple Rejection, or Supply Ripple?

Yes! PSRR (Power Supply Rejection Ratio) is all three! Power Supply Rejection Ratio is also referred to as Power Supply Ripple Rejection, but in the world of timing solutions, we typically take the simple route and refer to PSRR as supply ripple. In this post, we will use both terms, PSRR and supply ripple, interchangeably.

So what exactly is PSRR?

PSRR is a measure of how well a circuit rejects noise of various frequencies from a particular device’s power supply. More specifically, from a device’s voltage input. Optimally, if the voltage input of a device changes, the output should not change. Unfortunately, this is almost always not the case. The ratio of the power input to output is where we get PSRR. To find PSRR, simply take the change of input voltage divided by the change of output voltage.

The ripple can be caused by multiple sources including a switching ripple from a dc/dc converter, a 50Hz/60Hz supply ripple, or a ripple caused by the sharing of an input supply between multiple circuit blocks on the board.

The Circuit-Board Dilemma

Engineers and designers are often faced with the challenge of increasing the amount of functionality of a printed circuit board (PCB) while also making them smaller and more compact. Hardware designers typically do this by using a “cleaner” power supply; however, the board space required to implement power-supply filtering can increase the overall size and cost of the design. Without going into too much unnecessary detail, connecting multiple components to this clean power supply can result in direct jitter problems from just one device to all other devices. This can cause issues to arise for oscillators that haven’t even had ripple problems in the past. Stop the madness!

To make everything even more challenging, power-supply noise results in additional jitter or phase noise. Many frequency oscillators are tested only in low-noise environments, resulting in their sensitive nodes coupling noise. That coupled noise will translate into output jitter that will also oscillate at the fundamental oscillation frequency. To learn more about causes of jitter output and phase noise in your designs, check out this free guide.

How to Stop this Design Madness!

It's not as difficult as you may first think (as long as you take the easy way). Answer: Filters, filters, and more filters! A device’s supply ripple can usually be managed by applying a filter across the entire power supply. Even something as simple as adding a ferrite bead and discrete SMD capacitor (Low Pass Filter) will help tremendously. A linear regulator is another possible solution to filtering supply noise (used as a high-pass filter). In some cases, both filters acting as a low and high pass filter may be needed to filter over the entire frequency band of a given device. It's a good idea to implement an effective design review to determine which of these options are best for your application, if any at all.  

Luckily, the risk of high costs is on the engineer or hardware designer's side.

Let me explain...

The more a device’s performance quality increases, the more likely expensive external circuitry will be needed. Because of this, many timing device engineers have started incorporating internal circuits in their designs (such as PLLs, filters, and LDOs).

So why is this a good thing?

Because such internal circuits actually aid in controlling the supply ripple of the device.

But beware! Every system is different. Designs by a frequency control engineer may not always reduce or eliminate the observed supply ripple. Incorporating an all-encompassing filter circuit may also not be a good decision in the design. The oscillator may not work well in certain conditions, including conditions under an all-encompassing filter. Tests should be done before hand to make sure the oscillator will perform correctly under the given design conditions.

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