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Low-Power Mixer Hits High Intercept

Fabricated with 0.18-m RF CMOS technology, this downconversion mixer uses a current-reuse bleeding technique to achieve high linearity, while consuming only 6 mW from a +1.2-VDC supply.

Wireless communications in the 5.2-GHz band has gained a great deal in popularity in recent years, prompting an increased need for high-performance components at reasonable prices. In addition to good electrical performance, wireless systems designers also seek highly integrated circuits capable of operating at low voltages and low power levels.1 One of the key components for wireless applications in the 5.2-GHz band, such as wireless local area network (WLAN) transceivers, is the RF mixer. It is a critical component for achieving good linearity, although such performance typically requires higher power consumption. Fortunately, the authors developed a downconversion mixer for fabrication in 0.18-m silicon CMOS semiconductor technology that employs a current-reuse technique for enhanced power economy. It is designed to downconvert an RF input signal at 5.2 GHz to an intermediate-frequency (IF) output at 200 MHz while consuming only 6 mW power.

High-frequency mixers for wireless applications are often based on a conventional Gilbert cell mixer topology, owing to the benefits of an active CMOS mixer design (such as good port-to-port isolation and low even-order distortion).2 However, one of the limitations of a conventional Gilbert mixer is linearity, along with poor conversion gain and high power consumption because of the voltage-to-current conversion of the design's source-coupled device pair. There are three ways to overcome these limitations.3-5 Four PMOSFETs can be used as switches to form a folded mixer structure.3 This type of structure provides high conversion gain because of the folded structure, but still suffers from high power consumption because of its small injection current.

A low-voltage downconversion architecture with an LC tank circuit was reported in ref. 6. It allowed for a large output voltage swing because the LC tank reduced the voltage headroom problem, but the approach still required a relatively large chip size and suffered from narrowband operation. A low-voltage mixer design reported in ref. 5 featured decreased voltage and power consumption by means of its current enhanced and negative-resistance compensation, although the linearity was low. Many wireless designs require short stand-by times, low voltage, and low power consumption in order to minimize the size of the batteries required.6 So, in this proposed mixer, techniques of current injection and a current mirror were enlisted to decrease the operating voltage and increase the conversion gain. Current reuse and source-level feedback inductors were used to boost the linearity.

Designing a downconversion mixer involves numerous challenges, including achieving a good input impedance match, high voltage gain, low noise figure, high linearity, and low power consumption. For example, Fig. 1 shows a traditional downconversion mixer based on an active Gilbert-cell configuration.

For large conversion gain and high input third-order intercept point (IIP3) with low power dissipation, the RF stage is designed to operate in its saturation region while the LO stage should operate in a device off state. In this mixer topology, currents i1 and i2 can be found from Eqs. 1 and 2:

i1 = IRF + 0.5gm1VRFcos?RFt (1)

i2 = IRF + 0.5gm2VRFcos?RFt (2)

The output current can be found from Eq. 3:

iIF = (i3 - i4) - (i5 - i6) (3)

The conversion gain of the mixer can be approximated7 by Eq. 4:

Av gmRL(2/p)0.5
(Vgs - Vt)sw/(pVLO)> (4)

In Eq. 4, parameters gm and RL denote the transconductance of RF stage and the output load resistor, respectively. The term (Vgs - Vt)sw denotes the overdrive voltage of switch transistor. To achieve high IIP3 and conversion gain, a large current and load RL are necessary in the mixer architecture. Unfortunately, having a large current leads to high power consumption while a large load resistance, RL, can raise noise levels and decrease linearity, resulting in compromises in conversion gain, linearity, and power consumption.8,9

In a Gilbert cell mixer, the linearity is largely determined by the RF transconductance. As a result, a large part of the design effort is spent finding ways to establish a current mode of operation, such as by using degeneration resistors in the source. Unfortunately, source degeneration resistors will increase the noise level, degrading overall performance.

In contrast to a traditional mixer, the proposed mixer achieves high linearity and high conversion gain through the use of a four-layer structure. Figure 2 shows the proposed mixer circuit. In a traditional mixer circuit, the limited injection current yields only small conversion gain and low linearity. To increase the injection current, the proposed mixer architecture has a four-layer structure with series connected source level and current mirror circuit (M11 - M12). This approach not only improves linearity and conversion gain, but also reduces the required operating voltage and power consumption.10,11 PMOS transistors Mp1 and Mp2 provide the extra bleed current in the mixer circuit. The transconductance stage (M7 - M10) employs a current-reuse technique which can help improve conversion gain. To minimize the effects of noise, inductors L3 and L4 are used for source degeneration rather than resistors, which will also help improve the mixer's linearity12,13 The gate-source capacitance added by capacitors C3 and C4 to devices M1 and M2 helps reduce the matching inductance value required. At high frequencies, capacitors C1 and C2 can be approximated by a short circuit. The use of inductors L1 and L2 decreases the parasitic capacitances within the transconductance stage while also improving the mixer's noise and linearity performance. The resistive load RL is used to adjust the circuit to achieve conversion gain and output impedance matching.

The proposed low-power mixer was designed for and fabricated in a 0.18-m RF CMOS semiconductor process. It was simulated with the help of the SpectreRF computer-aided-engineering (CAE) software from Cadence Design Systems. Figure 3 shows the layout of the mixer cell. The mixer downconverts RF input signals at 5.2 GHz to an IF at 200 MHz by means of a 5-GHz local oscillator (LO) signal. Since power amplifiers are available in wireless transmit sections for increasing signal gain, a value of -1 dBm was chosen for the LO signal, resulting in 5.6-dB conversion gain in the mixer as shown in Fig. 4.

A measurement of the mixer's IIP3 performance was obtained by means of two-tone testing, with simulated IIP3 performance shown in Fig. 5. It was found to deliver an IIP3 of +14.3 dBm with 1-MHz RF input frequency spacing. Compared with a traditional Gilbert cell mixer, this new design provided linearity improved by about 5 dB. The table shows the performance and simulated results for the proposed mixer with several other mixers from recent literature studies. Figure 6 shows different noise-figure performance levels for different IFs. The noise figure at 200 MHz is about 13.8 dB.

In summary, the mixer achieved good linearity with promising performance for wireless applications in the 5.2-GHz band. The use of current bleeding helped boost linearity, without compromising power consumption, which was still excellent at only about 6 mW from a +1.2-VDC low voltage supply.


The authors would like to thank the Open Fund Project of the Key Laboratory of Hunan University (No. 10K016) and the tutor's valuable advice.


  1. G.R. Aiello and G.D. Rogerson, "Ultra-wideband wireless systems," IEEE Macro Magazine, Vol. 4, No. 2, June 2003, pp. 36-47.
  2. B. Gilbert, "A highly linear variant of the Gilbert mixer using a bisymmetric class-AB input stage," IEEE Journal of Solid-State Circuits, Vol. 32, No. 9, September 1997, pp. 14121423.
  3. Min Lin, Haiyong Wang, and Yongming Li, "A novel CMOS front-end circuit with low power, low noise and variable gain for 5-GHz WLAN applications." IEEE Circuits and Systems, Vol. 2, 2002, pp. 266-269.
  4. C.C. Tang, W.S. Lu, L.D. Van, and W.S. Feng, "A 2.4 GHz CMOS down-conversion doubly balanced mixer with low supply voltage," in Proceedings of the IEEE International Symposium on Circuits & Systems (ISCAS), Vol. 4, May 2001, pp. 794-797.
  5. Chang-Hsi Wu and Wen-Hui Huang, "A High-Linearity Up-Conversion Mixer Utilizing Negative Resistor," IEEE Signals Systems and Electronics (ISSSE) 2010, Vol. 2 , pp. 1-4.
  6. A Rofougaran, J.Y.C. Chang, M. Rofougaran, and A.A. Abidi, "A 1-GHz CMOS RF Front-End IC for a Direct-Conversion Wireless Receiver," IEEE Journal of Solid-State Circuits, Vol. 31, No. 7, July 1996, pp. 880-889.
  7. C. Rudell Jacques, "A 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications," IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, December 1997, pp. 2071-2088.
  8. S.G. Lee and J.K. Choi, "Current-reuse bleeding mixer," IEEE Electronics Letters, Vol. 36, No. 8, April 2000, pp. 696-697, April 2000.
  9. H. Darabi and A.A. Abidi, Noise in RF-CMOS mixers: A simple physical model, IEEE Journal of Solid-State Circuits, Vol. 35, January 2000, pp. 15-25.
  10. Ta-Tao Hsu and Chien-Nan Kuo, "Low Power 8-GHz Ultra-Wideband Active Balun," IEEE 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, January 2006.
  11. M. Rajashekharaiah, P. Upadhyaya, D. Heo, and E. Chen, "A New Gain Controllable On-Chip Active Balun for 5GHz Direct Conversion Receiver," IEEE International Symposium on Circuits and Systems, Vol. 5, May 2005, pp. 5115-5118.
  12. E. Roa, J.N. Soares, and W. Van Noije, "A Methodology for CMOS Low Noise Amplifier Design," IEEE Proceedings of the Symposium on Integrated Circuits and Systems Design, September 2003, pp. 14-19.
  13. T. Melly, et al., "An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers," IEEE Journal of Solid-State Circuits, Vol. 36, No. 1, January 2001, pp. 102-109.
  14. H. Feng, Q. Wu, X. Guan, R. Zhan, and A. Wang, "A 5-GHz Sub-Harmonic Direct Down-Conversion Mixer for Dual-Band System in 0.35-m SiGe BiCMOS," IEEE International Symposium on Circuits and Systems 2005 (ISCAS 2005), May 2005, pp. 23-26.
  15. R.K. Pokharel, Y. Yano, M.A. Abdelghany, H. Kanaya, and K. Yoshida, "Design of High Linearity Low Flicker Noise 5.2-GHz Down-Conversion Mixer for Direct Conversion Receiver," 2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), May 27, 2011, pp. 64-67.
  16. Tao Li, Fengyi Huang, Yan Wang, and Xinrong Hu, "A High Linearity Reconfigurable Down-Conversion Mixer for Dual-Band Applications," 2010 International Symposium on Signals Systems and Electronics (ISSSE), October 21, 2010, pp. 1-4.
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