Signal stability is critical to a wide range of communications systems, especially those that rely on low-jitter clock sources for data conversion. Systems operating with analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) depend on clock sources with low jitter in the time domain and low phase noise in the frequency domain. Fortunately, a six-page application note (AN513) from Silicon Laboratories, “Jitter Attenuation—Choosing the Right Phase-Locked Loop Bandwidth,” provides guidance on selecting a clock source for these systems and setting an optimum phase-locked-loop (PLL) bandwidth for the system.
High-frequency signal sources support and enable communications systems for increasingly higher frequency bands, including for point-to-point links at millimeter-wave frequencies. As digital communications systems move beyond rates of 40 Gb/s and analog systems move higher than 60 GHz, the challenges of designing and fabricating low-noise clocks and signal sources increase; inevitably, the data converters in these systems rely on stable reliable signals from the clocks and other signal sources.
PLL signal sources are often used in these systems and, as application note AN513 points out, even the most carefully constructed PLL signal source can be haunted by noise from two main sources: noise transferred from the frequency reference, and noise emanating from the tunable signal source [such as the voltage-controlled oscillator (VCO)]. Some of these noise components come from power-supply noise, from loop filter components in the VCO, and from noise in amplifier and other active-device components used to boost the amplitude of the VCO’s output signals.
The application note provides a brief review of PLL basics and how different parts of the PLL structure can impact the output jitter performance of the source. The loop filters, for example, are typically used to control the noise of a tunable signal source, but can also play a role in the jitter performance of the PLL source. Reducing the loop filter bandwidth will increase the amount of jitter attenuation on the PLL’s reference oscillator, transferring less jitter from the input to the output ports. As a result, a PLL designed with a somewhat “noisy” reference oscillator can be stabilized by using a low PLL bandwidth to filter the unwanted reference oscillator noise.
The relative contribution of the VCO’s noise to the overall PLL source jitter increases as the PLL loop bandwidth decreases. Unless the PLL employs a VCO with very low phase noise, the PLL designer faces the tradeoff in selecting a PLL bandwidth that will minimize both the VCO and the reference oscillator jitter contributions.
The six-page application note provides an example circuit based on one of the company’s jitter-attenuating clock devices. The clock features digital tuning and is relatively simply to add to the signal path of a PLL circuit design. It includes pin-controlled settings for loop filters from 60 Hz to 8.4 kHz, allowing designers to manage the tradeoff between transferred jitter and generated jitter, and choose a loop-filter bandwidth that helps them optimize PLL jitter performance at the application level. More details are provided in the application note, which is available for free download as a PDF from the company’s website.
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