Software-defined radios (SDRs) offer the flexibility and versatility needed to address the radio and communication needs of a multitude of applications and markets. They come equipped with high radio bandwidth, processing power, digital backhaul, and various radio channels to provide the performance sought by many industries to meet strict project goals. Addressing those needs, Per Vices offers Cyan, its latest SDR that it claims offers the highest bandwidth and largest number of independent radio channels available in a commercial-off-the-shelf (COTS) platform (see figure).
Cyan is a high-channel-count, ultra-wideband, high-gain, direct-conversion transceiver and signal-processing SDR platform that’s built in a compact rack-mount enclosure. It offers a tuning range of 100 kHz to 18 GHz along with up to 16 fully independent radio channels that constitute one’s choice of receive or transmit channels (i.e., the total number of receive and transmit channels can be as much as 16).
Each chain offers a standard 1-GHz bandwidth, allowing for a total bandwidth as high as 16 GHz if all channels are utilized. This performance is driven by high-speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) that both offer as much as 16 bits of resolution along with a top-of-the-line field-programmable-gate-array (FPGA) system-on-chip (SoC).
The Cyan SDR offers performance at frequencies as high as 18 GHz.
The Cyan SDR can operate within commercial and military radar, ground stations, (counter) electronic warfare, test-and-measurement, low-latency point-to-point links, and medical imaging applications and systems. It also offers spectrum-monitoring, signal-generation, data-processing, and data-transport capabilities, with host systems designed for advanced data storage and processing. In addition, Cyan is well-suited for spectrum recording and sensing by utilizing the flexible radio architecture in combination with a high bandwidth and a large number of channels.
With the option to use as many as 16 transmit channels, whereby data is sent over the 4- × 40-Gb/s qSFP+ ports, Cyan can support many advanced applications. It provides additional features, such as timed commands, triggering, and a large amount of FPGA resources, for all types of digital signal processing (DSP).
Superior Components Push Performance
The Cyan SDR can achieve impressive performance due to its implementation of high-quality components. On the digital front, it features the Intel Stratix 10 FPGA with an on-chip Arm Cortex-A53 MPCore processor, enabling various DSP functions and loading of IP cores to be performed on the FPGA. This reduces host-systems specifications, or in some applications, removes the need for a host system entirely.
Cyan was further designed to adhere to size, weight, and power (SwaP) requirements, measuring 482.6 × 402.0 × 133.0 mm in the standard form factor. Its size can be further reduced depending on the application.
The radio-front-end architecture consists of independent radio boards (either receive or transmit). The receive architecture includes a dual-channel ADS54J60 ADC that samples at 1 Gsample/s. Operation from 9 kHz to 18 GHz is possible with the radio-chain architecture. The radio board can be employed as many as 16 times to create 16 independent receive chains that each offer sampling of 1 Gsample/s.
The transmit radio board features the dual-channel AD9163 DAC that samples at 1 Gsample/s. Like the receive board, the transmit board supports operation between 9 kHz and 18 GHz. Cyan can support applications that require many transmit radio chains by utilizing up to 16 of these transmit radio boards. The radio chains combine some of the industry’s highest-performance converters and RF synthesizers with synchronization capability and phase coherency among all radio channels.
The timing architecture for Cyan relies on a stable (±5 ppb) and accurate 10-MHz signal delivered by an oven-controlled crystal oscillator (OCXO). Precise tuning from 100 kHz to 18 GHz is supported. The system also supports the use of an external reference clock, provided that the source meets system performance requirements.
The default configuration is factory-calibrated to provide a known (in-phase) deterministic relationship for all LMK04828 clock conditioner outputs. As a result, the leading edge of all outputs and internal VCOs can be synchronized at the reference inputs of all frequency synthesizers, converters, and transceivers.
High-performance SDR systems from Per Vices have been especially useful for applications that require high channel count and RF sampling rates. The company also offers full customization support if higher-performance systems are needed for a specific application. These services include custom hardware, firmware, and software integration support, as well as COTS Linux host systems. The latter enable rapid deployment and are specifically designed to meet data-storage and processing needs.
Brandon Malatest is Chief Operating Officer and Sausan Arebi is a Technical Writer at Per Vices.