Synchronized Synthesizers Aid Multichannel Systems

Sept. 20, 2005
Precise synchronization capability in a pair of direct-digital-synthesizer circuits supports the advanced signal-processing requirements of modern radar systems.

Direct-digital-synthesis (DDS)-based synthesizers are primarily known as agile frequency sources with low phase noise and excellent spurious performance. In many applications, they offer significant advantages over phase-locked-loop (PLL) synthesis methods like sub-hertz frequency tuning resolution, phase offset, and output amplitude control. With multiple source channels and synchronization capability now built into a pair of commercial DDS products—the four-channel AD9959 (Fig. 1) and the two-channel AD9958 from Analog Devices (Greensboro, NC)—multiple signal generation can now be performed with precise timing and phase control.

Both synthesizers are 10-b, 500-MHz integrated circuits (ICs). The AD9959 employs four complete DDS channels on one chip. A complete DDS channel consists of the digital waveform generator, digital-to-analog converter (DAC), and application-specific control logic. In addition to the four independent DDS channels of a single AD9959, the synchronization of multiple products is facilitated via dedicated pins that are specifically designed to automatically synchronize multiple AD9959s. This feature provides a convenient method to synchronize an unlimited number of channels when multiple chips are used. The AD9958 is a two-channel version of the AD9959 with similar features and performance specifications.

Even though DDS technology offers excellent frequency and phase tuning characteristics, upconversion is required to take advantage of these features at UHF or microwave frequencies. Various methods of upconversion are commonly used. In one method, the DDS is in the feedback loop of a PLL (Fig. 2). This approach has limitations that can be overcome by employing a design configuration that uses two DDS channels in quadrature to suppress sideband energy (Fig. 3).

In the circuit design of Fig. 2, many of the advantages of the DDS are limited by the PLL. For example, the fast frequency-hopping capability of the DDS is limited by the lock time of the PLL. Any spurs or phase noise from the DDS that are within the loop bandwidth of the PLL are increased by the loop gain and transferred to the PLL output. For these reasons, the architecture is typically limited to systems that generate a single tone or operate with lower-bandwidth transmission.

Figure 3 shows a design architecture in which the two DDS channels are upconverted using a mixer stage. It also illustrates where two DDS channels with independent phase and amplitude control are ideal for systems operating at higher data rates. With this method, fast frequency hopping is preserved. Faster data rates are therefore allowed. The primary concern with upconverting a signal using a mixer is the creation of a redundant sideband, which tends to be difficult or impractical to filter. By using the DDS to send quadrature signals to the in-phase and quadrature (I and Q) inputs of an analog quadrature mixer, the redundant sideband can be attenuated significantly. This approach relaxes the filtering requirements.

The AD9959/58 provides independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct the imbalances between quadrature signals due to analog processing like filtering, amplification, or PCB-layout-related mismatches. All channels are inherently synchronized because they share a common system clock, effectively eliminating the need to synchronize multiple devices. With a single-chip solution, the temperature effects that exist between two separate devices are essentially eliminated as well.

Lab results have shown that the AD9959/58 device enables better than –60-dBc suppression of the redundant sideband. The two plots of Fig. 4 (4a, 4b) show the results of a 25-MHz, single tone that is upconverted to 975 MHz. Suppression of the upper sideband, when employing quadrature signals from the AD9959, is shown in plot (b). Figure 5 (5a, 5b) shows the results of FSK-encoded data. There, plot (a) does not employ quadrature signals from the AD9959 but plot (b) does. Note that when using the analog quadrature mixer architecture, feedthrough of the local-oscillator (LO) frequency may occur. Minimizing this feedthrough was not addressed in the lab experiments shown in Figs. 4 and 5.

DDS Radar Applications
Traditionally, early radar systems consisted entirely of analog circuits. More recently, radar designers have been adopting digital techniques that are reducing cost while increasing the capabilities of the system. DDS technology is now routinely found in radar-system designs. The DDS characteristics that most attract radar-system designers are precision frequency tuning, phase offset control, and linear "chirp" capability. Two types of radar that typically incorporate DDS devices are pulsed and frequency-modulated continuous-wave (FMCW) radar.

Recent studies indicate that many radar systems use multiple DDS channels, which require synchronization to one another. This requirement also includes proper clock distribution for each DDS device. In some pulsed radars, the number of radiating elements (antenna) can range from a few up to a hundred or more. The antennas are fashioned in an array, which is used to electronically steer the transmitted radar beam. This approach is referred to as "phased-array radar." This can be accomplished by assigning a DDS channel to each individual antenna in the array. Its phase adjustment is the mechanism for steering the beam. In all cases, the beam steering has all DDS channels operating at the same output frequency. It uses the phase-offset feature to accomplish the task of beam steering.

Compared to pulsed radar, FMCW radar is more challenging to use with a phased-array antenna. In this configuration, the beam is harder to steer due to the constantly changing phase differences that are required as the signal is chirped in frequency. To overcome this challenge, phase adjustments of the FMCW signal must be performed to each FMCW signal during the chirp period. In previous DDS designs, simultaneous changes to these parameters did not appear at the digital-to-analog-converter output simultaneously because of internal waveform-generation pipe stages. However, the AD9959 includes a matched latency feature that allows frequency, phase, and amplitude changes to occur simultaneously.

Figure 6 (6a, 6b) shows the difference between a pipe-matched DAC output and a non-pipe-matched output. The frequency and amplitude were cut by 50 percent and the phase changed by 180 deg. Plot (a) clearly shows that amplitude changes before phase and frequency. In plot (b), the pipe-matching switch is active. The DAC output changes frequency, phase, and amplitude simultaneously. Note that these plots were taken on the unfiltered DAC output to better show the effect of latency matching. The output therefore appears to be "stair-stepped."

A recent study concluded that more than 50 percent of all DDS-based designs employ more than one channel. Almost 75 percent of those systems require synchronization between channels. In addition, nearly 15 percent of the multichannel systems require more than four channels. Multiple devices are considered synchronized when the state of the internal clock-generation state machines are identical for all parts. The SYNC_CLK output pin for each device will then be in phase with each other. Multiple-part synchronization can be achieved by a simple connection of the SYNC_OUT pin on the master device to the SYNC_IN input of the slave device(s). Devices are configured as master and slaves through programming bits, which are accessible via the serial port.

In Fig. 7, the sync pulse is sent from the master to the "Synchronization Delay Equalization" circuitry outside the AD9959/58 chip. The goal is to simultaneously distribute this pulse to the SYNC_IN pins of the slave device(s). The slave device(s) sample the synchronization pulse from the master and compare the clock-generation, state-machine current state against an "expected" value. If the slave device's clock-generation state machine compares properly with that value, the devices are synchronized. If the slave device's clock-generation state machine and the expected value are not identical, the device stalls the clock-generation state machine for one system-clock cycle.

This sample/compare/act procedure runs continuously as long as the devices are configured for synchronization. Say, for example, that the slave devices were to become unsynchronized due to a temporarily corrupted reference-clock input. The slave devices will automatically re-synchronize to the master once the reference clock becomes stable.

The astute reader may consider that at high system-clock rates, it may be difficult to propagate the synchronization pulse from the master device to the slave devices in one system-clock cycle. To facilitate synchronization at high rates, the user is given the ability to program the slave device. It can be programmed to expect the synchronization pulse from 1 to 16 system-clock cycle periods after being generated by the master. This task is accomplished by programming the slave devices via the serial port with the incremental, external propagation delay expected on the synchronization pulse. Another benefit of this feature is that each slave device can be programmed to differing "expected states," which allows for more tolerance in the synchronization pulse distribution circuitry.

In addition to the automatic synchronization mode, the AD9959/58 offers manual synchronization modes under direct user control. Both hardware and software manual synchronization modes are available. The hardware manual synchronization mode allows the user to stall the devices' clock-generation state machine for one system-clock cycle for each rising edge (logic 1) detected at the SYNC_IN pin. In the software manual mode, a specific bit is written via the serial port. That bit causes the devices' clock-generation state machine to stall for one system-clock cycle. As a result, the phase relationship between the system clock and the SYNC_CLK output signal is changed in single system-clock period steps.

A key specification in multi-channel systems is channel-to-channel isolation. Without proper isolation, AC performance may be significantly degraded. Figure 8 displays lab results of typical channel-isolation performance for the AD9959. The measurements were taken on a single channel that was generating a 110.3-MHz tone, while the other three channels were sweeping from 25 MHz to 200 MHz. The difference between the energy level at 110.3 MHz and that seen at the other channel's frequency is the channel-to-channel isolation. Better than –65 dBc was recorded for all possible cases. The two-channel AD9958 device has better isolation by more than –6 dBc for identical tests.

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