In millimeter-wave phase-locked loops (PLLs), the following divider chain must meet demanding performance requirements. An injection-locked frequency divider (ILFD) can be a good choice for these PLLs for its high input sensitivity, low power, and high speed. In addition to suffering from a limited locking range, however, it is sensitive to process variations. At National Taiwan University, Pin-Hao Feng and Shen-Iuan Liu investigated divide-by-3 ILFDs, proposing one with second-harmonic peaking to enhance the locking range.
Their four divide-by-3 ILFDs are fabricated in 40-nm CMOS technology. A distributed inductor technique is used to enhance both operating frequency and locking range. Among those four dividers, the largest measured locking range is 236.6~245.3 GHz. Operating frequencies reached beyond 280 GHz. All four ILFDs consume 2.97~3.96 mW from a 1.1-V supply, excluding output buffers.
The proposed divide-by-3 ILFDs are realized by a NMOS cross-coupled pair, two injection-locked NMOS transistors, a PMOS current source, and three inductors. To generate the second harmonic, two injection-locked transistors are connected in series and act as the mixers. That harmonic is further enhanced by the addition of a peaking inductor to a parasitic capacitor. To save on area, the researchers found that a rectangular-shaped inductor was a better choice than a square one. Among the products of this research are G-band (140~220 GHz) and H-band (220~325 GHz) divide-by-3 ILFDs, which can be used in a millimeter-wave PLL over 200 GHz for point-to-point applications. See “Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS,” IEEE Journal Of Solid-State Circuits, Feb. 2013, p. 405.
