Modular SoC Design Integrates RF Transceiver In 32-nm Process

April 29, 2013
This system on a chip (SoC) integrates diverse digital, analog, and RF blocks on a single die, allowing the RF transceiver and associated RF front end to co-exist with the rest of the SoC while maintaining RF performance.

Because of incompatible process features and the challenges of managing system noise, the RF portion of a WiFi radio still tends to be an external personal-computer (PC) component. Impressively, however, researchers at Intel Corp. have created an integrated, standard x86 operating-system-compliant, dual-core ATOM-processor-based system-on-a-chip (SoC) that includes the WiFi RF transceiver. This SoC is designed for rapid integration and customization for specific market segments. As such, it boasts a multi-source intellectual-property (IP) ecosystem, which comprises both modular and configurable building blocks.

A standardized SoC interface is used to reduce design time while allowing the integration of diverse IP blocks. It implements a custom interconnect fabric called Intel On-Chip System Fabric (IOSF), which provides a standardized interface supporting signaling, decoding, flow control, and power management of IP. It also can support industry-standard buses. 

During 2.4-GHz IEEE 802.11g operation, the RF transceiver offers receive sensitivity of -74 dBm, an input third-order intercept point of -8 dBm, and transmit output power of +20.3 dBm (-25 dB error vector magnitude) at 14% transmit RF efficiency. Boosting integration, the SoC houses PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, a memory controller, and the RF portion of the WiFi transceiver. This feat is managed in a 32-nm high-k/metal-gate RF CMOS process fabricated on a high resistivity substrate.

This impressive development is the brainchild of the following individuals: Hasnain Lakdawala; Mark Schaecher; Chang-Tsung Fu; Rahul Limaye; Jon Duster; Yulin Tan; Ajay Balankutty; Erkan Alpman; Chun C. Lee; Khoa Minh Nguyen; Hyung-Jin Lee; Ashoke Ravi; Satoshi Suzuki; Brent R. Carlton; Hyung Seok Kim; Marian Verhelst; Stefano Pellerano; Tong Kim; Satish Venkatesan; Durgesh Srivastava; Peter Vandervoorn; Jad Rizk; Chia-Hong Jan; Sunder Ramamurthy; Raj Yavatkar; and Krishnamurthy Soumyanath. See “A 32 nm SoC with Dual Core ATOM Processor and RF WiFi Transceiver,” IEEE Journal Of Solid-State Circuits, Jan. 2013, p. 91.

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