14-nm Test Chip Eyes FinFET Process

Jan. 9, 2013
ARM and Cadence Design Systems announced the tape-out of the first 14-nm test chip implementation of the ARM Cortex-A7 processor.

To support the continuous move to high-density, high-performance, and ultra-low-power systems-on-a-chip (SoCs) for future mobile devices, Samsung is preparing its 14-nm FinFET process. Last month, ARM and Cadence Design Systems, Inc. announced the tape-out of the first 14-nm test-chip implementation of the ARM Cortex-A7 processor. In addition to that processor, the test chip includes ARM Artisan standard-cell libraries, next-generation memories, and general-purpose input/output connections (I/Os).

Designed with a complete Cadence register-transfer-level (RTL) -to-signoff flow, the chip is the first to target Samsung’s 14-nm FinFET process. The test chip was designed using Cadence’s Encounter RTL Compiler, Encounter Test, Encounter Digital Implementation System, Cadence QRC Extraction, Encounter Timing System, and Encounter Power System. The achievement of the test chip is part of a systematic program to enable ARM technology-based SoCs on FinFET technology.

About the Author

Nancy Friedrich | RF Product Marketing Manager for Aerospace Defense, Keysight Technologies

Nancy Friedrich is RF Product Marketing Manager for Aerospace Defense at Keysight Technologies. Nancy Friedrich started a career in engineering media about two decades ago with a stint editing copy and writing news for Electronic Design. A few years later, she began writing full time as technology editor at Wireless Systems Design. In 2005, Nancy was named editor-in-chief of Microwaves & RF, a position she held (along with other positions as group content head) until 2018. Nancy then moved to a position at UBM, where she was editor-in-chief of Design News and content director for tradeshows including DesignCon, ESC, and the Smart Manufacturing shows.

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