14-nm Test Chip Eyes FinFET Process

Jan. 9, 2013
ARM and Cadence Design Systems announced the tape-out of the first 14-nm test chip implementation of the ARM Cortex-A7 processor.

To support the continuous move to high-density, high-performance, and ultra-low-power systems-on-a-chip (SoCs) for future mobile devices, Samsung is preparing its 14-nm FinFET process. Last month, ARM and Cadence Design Systems, Inc. announced the tape-out of the first 14-nm test-chip implementation of the ARM Cortex-A7 processor. In addition to that processor, the test chip includes ARM Artisan standard-cell libraries, next-generation memories, and general-purpose input/output connections (I/Os).

Designed with a complete Cadence register-transfer-level (RTL) -to-signoff flow, the chip is the first to target Samsung’s 14-nm FinFET process. The test chip was designed using Cadence’s Encounter RTL Compiler, Encounter Test, Encounter Digital Implementation System, Cadence QRC Extraction, Encounter Timing System, and Encounter Power System. The achievement of the test chip is part of a systematic program to enable ARM technology-based SoCs on FinFET technology.

About the Author

Nancy Friedrich | Editor-in-Chief

Nancy Friedrich began her career in technical publishing in 1998. After a stint with sister publication Electronic Design as Chief Copy Editor, Nancy worked as Managing Editor of Embedded Systems Development. She then became a Technology Editor at Wireless Systems Design, an offshoot of Microwaves & RF. Nancy has called the microwave space “home” since 2005.

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