# Digital Predistortion Linearizes Broadband PAs, Part 2

Aug. 13, 2008
This efficient and flexible Volterra-based adaptive predistortion technique can be used to achieve high linearity in broadband RF power amplifiers.

Power amplifiers (PAs) are essential to the transmitter sections of communications systems and in many other RF/microwave applications. As seen last month in Part 1 of this three-part series, the linearity of a power amplifier is often compromised for efficiency, but numerous digital predistortion techniques are available to help improve linearity without sacrificing efficiency. Part 2 of this threepart article series will offer some comparisons of different wireless communications signals with and without the use of digital predistortion while, in September, Part 3 will highlight specific improvements made in the linearity of amplifiers and their boosted signals in Third-Generation Partnership Program (3GPP) systems. Referring back to the first several equations in Part 1 (July Microwaves & RF), the Volterra series in Eq. 1 was simplified to the form of Eq. 3 by ignoring the effects of memory on the PA and including only nonlinear diagonal terms, resulting in Eq. 3. If the memory effects are included, it assumes the form of Eq. C from Part 1 of this article, reducing the equation to a finite-impulse-response (FIT) form. For some types of RF/microwave PAs, additional memory effects are dependent upon the signal envelope history of the amplifier. They can be due to thermal effects or power-supply transients that act nearly as multiplicative gain that is a function of the amplifier's power history. Considering the terms from the Volterra series in Eq. 1 that involve cross products between the signal and its exponentiated envelope (and excluding terms already covered by Eq. 3) yields

It can be seen that most of the terms in this desired memory model involve single-dimensional convolutions of the signal envelopes |x(n)|2,|x(n-i)|4 and |x(n-i)|6 and can be well implemented using FIR filters.

The nonlinear DPD implementation in the GC5322 provides a programmable memory depth between 10 and 60 ns depending on the clock rates chosen, and typically uses a polynomial order in the range of 3 to 15 (depending on the amplifier type) to model the nonlinearity. Interpolating LUTs are used in the GC5322 predistorter to model complex highorder polynomials, resulting in high dynamic range.

The third major block in the GC5322 is the feedback nonlinear compensator and smart capture buffers. Referring to Fig. 2, the feedback signal from the power amplifier is used to compute the instantaneous error, which along with the reference transmit signal can be captured in a pair of on-chip memories. These captured signals can be read back by the DSP processor that implements the adaptation algorithms for the pre-distorter blocks. Different signal metrics (like average signal levels, or peak content), are monitored and can trigger a capture when an optimum data set is collected. This programmable datamonitoring technique helps the adaptation algorithms to converge faster and prevents it from diverging in the absence of suitable transmit data. An 8-tap complex linear equalizer and a nonlinear compensator consisting of a complex multiplier and a look-up table help compensate for distortions in the RF/analog feedback signal chain.

A 150-W Doherty PA with significant memory effects for a 20-MHz high PAR OFDMA-based system might require all of the above predistorter blocks to achieve optimum linearization. Whereas a smaller 5-W Class AB PA for a 5-MHz low-PAR application might do well with only one of the LUTs in the nonlinear DPD block active, and without any adaptive compensation in order to minimize cost. The predistorter implemented in the GC5322 is intended to be flexible enough to work with a variety of PA models, and comprehensive enough to account for a majority of PA nonlinear effects while still keeping complexity low for real-time adaptation.

A direct-learning architecture was used in the predistortion adaptation algorithm implemented on a TI C67x DSP. A model of the predistorter is maintained in software, and its parameters optimized to minimize the error signal captured in the hardware. The adaptation algorithm periodically reads back the captured signals from the hardware capture buffers, and uses them to train the pre-distorter model. The optimized predistorter parameters are then regularly updated back to the hardware. Square-root Kalman-filterbased minimization algorithms are used to adapt the predistorter model parameters so as to minimize the parameter RMS error. The frequency of updates required to the DPD parameters depend on the PA topology and its operating conditions. More details on these adaptation algorithms will be presented in a future article.

The GC5322 evaluation platform (Fig. 3) was used to test the capabilities of the pre-distortion hardware. A variety of different RF architectures can be supported by the GC5322 . The evaluation platform used to compile the results presented here consists of a GC5322 evaluation module (that includes a TI C6727 DSP), and two different versions of TI reference RF up/downconversion boards, a "WiMAX" and a "WCDMA" version, both with low IF, analog quadrature modulation and a common LO for the transmit and feedback paths. More details on the architecture are listed in the table.

For performing experiments on the effectiveness of the new DPD circuit, a three-stage PA consisting of a 2-W predriver from Sirenza Microdevices (recently acquired by RF Microdevices, www.rfmd.com), a 45-W NXP Class AB driver stage from NXP Semiconductors (www.nxp.com), and a 130-W LDMOS Doherty PA from NXP Semiconductors (with +55-dBm output power at 2-dB compression at 2.1 GHz) was used in all cases.

Standard 3GPP test model signals (TM3-32 and TM1-64) were used as baseband data in these tests. Experiments were run at different PA output power levels (+42.75, +44.75, and +46.75 dBm>, PARs (6 and 7 dB), and signal types (TM1-64, TM3-32).

Figures 4(a) and 4(b) show the adjacent- and alternate-channel leakage power ratios (ACLRs) before and after the DPD for TM1 and TM3 test model data at 6- and 7-dB PARs. For pre- DPD amplification, the 3GPP ACLR requirement of -45 dBc is violated by more than 15 dB. For post-DPD amplification, these requirements are met with more than 5-dB margin for all these two-carrier WCDMA test cases.

Figures 5(a) and 5(b) show the pre- and post-DPD spectra for the +46.75-dBm, 6-dB PAR case for TM1-64 data. The worst-case (of the left and right sides) adjacent- and alternate-channel ACLRs are -26 and -34 dBc, respectively, before DPD. After DPD, the adjacent- and alternate- channel ACLRs are -53 and -59 dBc, respectively.

Figures 6(a) and 6(b) show the preand post-DPD peak-code-domain-error (PCDE) and EVM metrics for different combinations of output power, PAR, and signal types. In all cases for post-DPD amplification, the experiments met the 3GPP specifications of -33 dBc and 17.5 percent, respectively, with considerable margins.

Next month, the final installment of this three-part article series on linearizing broadband PAs through the use of digital predistortion will offer evidence of the effectiveness of the approach based on measurements made with test signals emulating a variety of different wireless communications standards, including with WCDMA, OFDM, and TD-SCDMA signals.

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