400-MSamples/s DDSs Run On Only +1.8 VDC

Dec. 1, 2002
This line of highly integrated DDS ICs features on-board RAM and crystal-oscillator circuitry to simplify the generation of agile and exotic waveforms.

Direct-digital synthesizers (DDSs) are flexible integrated circuits (ICs) capable of answering a host of design challenges. Programmable DDS ICs are agile frequency sources capable of low phase noise and good spurious performance. Until now, DDS performance has been saddled with a trade-off between clock rate or tuning resolution and power consumption. But the new 9954 DDS IC and other members of the 995X DDS families offer maximum update rates to 400 MSamples/s without turning up the power—only 180-mW power is consumed for the 9954 at 400 MSamples/s. The new DDS ICs are well-suited for frequency-agile frequency-shift-keying (FSK) and phase-shift-keying (PSK) modulators, as well as radar applications and any other commercial and military designs requiring fast-switching speeds with high frequency resolution and low phase noise.

The flagship of the new DDS product line is the model AD9954, with swept-frequency capabilities, precise amplitude control, multiple profile selection, on-chip 1024 × 32-b random-access memory (RAM), and an integral 14-b digital-to-analog converter (DAC). The IC also includes a phase-locked-loop (PLL) clock multiplier, on-chip crystal oscillator, and a high-speed comparator. Despite its functionality, the AD9954 is designed to operate on a mere +1.8 VDC. A 32-b phase accumulator at the heart of the AD9954 DDS core (Fig. 1) provides fine tuning resolution (0.093 Hz for a 400-MHz clock). Essentially, a DDS constitutes a sophisticated numerically controlled oscillator (NCO) that works by incrementing in a controlled manner a value representing the phase of a sinusoidal waveform. The phase accumulator acts as a modulus M counter and adds a delta-phase word to the existing phase with each clock cycle. The average rate at which the phase accumulator overflows determines the frequency of the generated signal and depends on the magnitude of the delta-phase word. The frequency is derived from the system-clock frequency and the capacity of the phase accumulator (232) according to the formula f0 = (Tfs) /232, where:

T = the value of the frequency tuning word or delta-phase word (0 ≤T ≤231),
f0 = the output frequency, and
fs = the system clock frequency.

Changing the frequency-tuning word of a DDS results in a phase-continuous output frequency that changes immediately. The addition of the phase-offset register provides further control of the accumulator and is a means to shift the phase of the output sinusoid under digital control. The output of the phase accumulator does not directly represent the amplitude of a sine wave. Therefore, following the phase accumulator, a phase-to-amplitude conversion circuit, represented by the cos(x) block in Fig. 1, processes the phase-accumulator result. The output of the phase-to-amplitude conversion represents a digital sine wave that the DAC converts to an analog signal. The phase accumulator generates the digital signal with 32 b of phase information, resulting in a tuning resolution of less than 1 Hz.

The 32-b phase accumulator yields far more phase resolution than can be resolved by a 14-b DAC. If all 32 b representing phases were converted to amplitude, an enormous amount of logic would be required. Therefore, to reduce circuit complexity and to save die area and power, designers commonly truncate the phase information before presenting it to the phase-to-amplitude conversion logic. Truncation leads to a systematic phase error in the signal and the error shows up in the DDS spectrum as spurious energy. The accumulator size, the phase word after truncation, and the tuning word determine the magnitude of these spurious products. As long as the spurious-free dynamic range limitation due to these spurious products remains below that afforded by the DAC, the DDS core does not become a performance restraint. Although the DDS generates frequencies with the 32-b phase accumulator to achieve high tuning resolution, much of the least-significant-bit (LSB) information is superfluous to the DAC. Since the DAC limits spurious performance to a 14-b level, the phase information can be safely truncated without loss of performance. The result is a highly tunable frequency generator with the ability to switch from one frequency to another almost instantaneously, while maintaining continuous phase and good spectral performance. In addition to its high resolution, the AD9954 includes dithering of the signal phase to improve the spurious performance at offsets close to the output frequency. The randomization of the LSBs of each phase word reduces spurious signal power due to the phase truncation that occurs just before the cos(x) block converts the phase.

The AD9954 includes 1024 × 32-b RAM, which can be powered down when not required for an application. When enabled, the RAM's output drives either the phase accumulator or the phase-offset adder. When the RAM drives the phase accumulator, users provide frequency-tuning words through RAM addresses and control the phase of the output by programming the phase-offset register. Programming the RAM to drive the phase-offset adder means the contents of the frequency-tuning-word register sets the DDS output frequency and the contents of the RAM determine its phase. The ability to choose where the RAM contents go makes programming the DDS for PSK modulation nearly identical to FSK modulation. Additionally, the RAM can be separated into four distinct addressable segments, enabling symmetrical or nonsymmetrical phase and frequency sweeping.

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The RAM operates in one of five modes: direct switch, ramp up, bidirectional ramp, continuous bidirectional ramp, and continuous recirculation. The direct-switch mode enables easy implementation of FSK or PSK modulation schemes. To design a four-tone FSK modulator, the RAM is split into four segments, with each segment containing a frequency-tuning word. Each segment receives a unique beginning address. Switching the profile-select pins to a particular binary value selects the tuning word from the contents of the RAM segment corresponding to that value. RAM segment 0 corresponds to 00 on pins PS; RAM segment 1 corresponds to 01 on pins PS, and so on. The FSK data presented to the profile pins modulates the output accordingly. Two-tone FSK requires data only on one profile select pin. To accomplish PSK modulation the user would program the RAM to provide the phase-offset word and the frequency-tuning-word register would control the output frequency. Data at the profile pins would then modulate the phase of the output, rather than the frequency.

In radar applications, the ramp-up mode permits users to program the RAM with up to four different sweep profiles when using RAM segmentation. The beginning address of each segment stores the sweep-starting frequency, and successive addresses contain the desired frequency-tuning words comprising the sweep profile. A programmable ramp-rate counter sets the speed at which the sweep occurs. As in the direct-switch mode, the state of the profile-select pins determines which sweep occurs, and the sweep begins when the DDS detects a change in the profile pins or when the user strobes the frequency-update pin. Furthermore, a "no-dwell" bit controls the behavior of the DDS output when the sweep reaches the terminal frequency. With the "no-dwell" bit set true, when the output reaches the terminal frequency the phase accumulator clears once the ramp-rate counter times out.

The bidirectional ramp mode enables symmetrical frequency or phase sweeps using a control signal applied to the PS pin. The part ignores signals applied to pin PS and the state of pin PS determines the direction of the sweep. With PS asserted high, the RAM address generator increments to the next address after the ramp-rate timer counts down to 1. If the input to PS remains in a low logic state, the address generator decrements the RAM address generator at a rate that is consistent with the ramp-rate counter. The continuous bidirectional ramp mode operates similarly to the bidirectional ramp, but implements an automatic sweep and repeating symmetrical frequency sweep between two frequencies. The ramp up and ramp down no longer begins coincident with a change in the control pin. Instead, the sweep up and sweep down occurs automatically at the ramp rate.

Finally, in the continuous recirculation mode, the RAM address generator repeatedly cycles through each address in "first-to-last" order. This mode permits automatic and continuous sweeps between two frequencies. From the initial address, the RAM address generator increments at the ramp rate until reaching the terminal frequency in the RAM segment-ending address. Once the RAM drives the frequency-tuning-word data in the final address the address, generator resets and the cycle repeats.

The RAM can store enough frequency tuning words (up to 1024) for a wide range of frequency sweep patterns (Fig. 2). The contents can drive the phase accumulator or load the phase-offset register to yield phase-modulation and phase-sweep patterns as well. Although linear sweeps are possible using the RAM, the RAM size limits the resolution of the sweep to 10 b (Figs. 2c and 2d). Therefore, executing higher-resolution linear sweeps involves an additional mode of operation.

Along with the RAM, additional digital circuitry provides further phase- and frequency-sweep capability, output-amplitude control, multiple DDS synchronization, and support for +5-VDC digital input/output (I/O) signals. The linear-sweep mode is capable of providing frequency sweeps of finer resolutions over a wider range than achievable when using the RAM-based sweep modes. A user simply programs the part with two frequency-tuning words and a delta-frequency-control word to linearly ramp between the two frequencies. The linear-sweep function, coupled with the output-amplitude control, provides a convenient way to implement nonsymmetrical frequency sweeps with precise amplitude control. The output multiplier included in the AD9954 design also allows output-shaped-keying (OSK) or on-off-keying (OOK) modulation formats. The amplitude can be programmed to automatically ramp between two values, and the user determines the value to which the output returns when the ramp completes.

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A clock output (SYNC OUT) that coincides with the clock in the DDS core enables users to align precisely the phases of output frequencies on two separate chips as a means of synchronizing multiple DDS devices to a common reference signal. The SYNC OUT signal from a master device feeding the SYNC IN port of a slave device arranges the two so that the user exercises some control over the phases of the clocks driving the phase accumulators. A self-clearing bit in the control register adjusts the phase of the slave device by one-quarter SYNC CLK cycle each time it is set. The precise alignment of the DDS clock on separate chips implies the ability to align and control the frequency sweeps originating from two separate devices. Figure 3 shows the block diagram of a possible radar application using two synchronized devices. The application-specific IC (ASIC) initiates frequency sweeps in both DDS devices with a controlled phase offset of 90 deg. The quadrature modulator following the DDS upconverts the sweep to RF.

The AD9954 includes a DAC, a PLL-based reference-clock multiplier, a comparator, and an oscillator. The 14-b DAC provides 10-mA full-scale current and drives the analog output to a 512-mVpp differential swing when terminated with 25-Ω resistors. This essential component of the complete DDS provides the analog signal needed for system components. An off-chip reconstruction filter is often used to remove image frequencies from the DAC spectrum and, with a carefully managed frequency plan, excellent spurious performance can be attained.

The DDS and DAC may be driven directly from an external clock signal, or a low-frequency clock can be multiplied by up to 20 times using the integrated clock multiplier. The AD9954 sports an integer-N PLL that multiplies input clock frequencies between 4 and 100 MHz to provide system-clock frequencies from 80 to 400 MHz. The PLL provides a convenient way to generate system clock frequencies to 400 MHz without requiring an expensive clock-generation circuit that is external to the part. For additional flexibility, the charge-pump current is programmable from 75 to 150 µA in 25-µA increments; with two voltage-controlled-oscillator (VCO) gain ranges, the user controls much of the loop characteristics of the system-clock generation. A programmable divider sets frequency multiplication between 4 and 20.

The on-chip oscillator works with crystals from 20 to 30 MHz. Placing a crystal (and only two additional capacitors) on the clock-input pins and enabling the oscillator circuit further simplifies the DDS system-clock generation. An output pin also provides a clock signal at the frequency of the crystal oscillator. With minimum effort, two or more AD9954s or other system components can be driven with one low-cost crystal, while maintaining a constant phase relationship between the components. Using its on-chip comparator, the AD9954 can generate square-wave clock signals at frequencies to 160 MHz. In a typical application, a lowpass filter between the DAC outputs and the inputs of the comparator removes unwanted out-of-band spectral content. The filter reconstructs a sinusoidal waveform from the DAC's sampled output and provides a spectrally clean input to the comparator, which squares the sine wave and produces a low-jitter clock source.

The practical output-frequency limit of the AD9954 is approximately 160 MHz. It is the company's first general-purpose DDS to offer a 14-b DAC for outstanding spurious-free-dynamic-range (SFDR) performance. The wideband SFDR measures up to 71 dBc, while the narrowband SFDR measures up to 85 dBc (Fig. 4). Integral nonlinearity measurements indicate the DAC is accurate to at least 12 b and differential-nonlinearity (DNL) accuracy is 13 b. All this performance is achieved while operating on a single +1.8-VDC supply with maximum power dissipation of less than 180 mW. A proprietary DDS algorithm allows much of the digital circuits to operate at clock frequencies lower than that of the DAC, providing tremendous power savings. With all features enabled and operating at the full clock rate of 400 MSamples/s, the AD9954 consumes less than 1/23 the power of the AD9852/54, the company's other two DDS products with frequency sweep capabilities. Yet, its phase-noise performance is on a par with much higher-power units (Fig. 5), approximately −145 dBc/Hz offset 100 kHz from a 98-MHz carrier. The phase-noise floor reaches −150 dBc/Hz at offsets greater than 1 MHz.

Integrating over the 1-Hz-to-10-MHz bandwidth, the AD9954 contributes about 0.6 ps of root-mean-square (RMS) jitter. In some applications, noise in the 1/f2 region may dominate system performance and low-frequency noise may not be a critical concern. In Fig. 5, the 1/f2 noise region corresponds roughly to the band from 1 to 100 kHz. A second jitter estimate based on this portion of the phase noise measurement suggests the AD9954 would contribute less than 0.2-ps RMS jitter.

The AD995X family of DDS ICs (see table) is supplied in 7 × 7-mm 48-lead TQFP packages with an exposed paddle. In addition to the AD9954, the family includes the AD9859, the AD9951, the AD9952, and the AD9953, all of which are capable of 400-MSamples/s operation. In addition, an evaluation board populated with two DDS ICs and a personal-computer (PC) software control interface will be available upon release. P&A: $9.75 to $17.25 (1000 qty.); 90 days. Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106; (800) 262-5643, (781) 329-4799, FAX: (781) 326-8703, Internet: www.analog.com.

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