DDS IC Initiates Synchronized Signals

July 20, 2005
These integrated circuits (ICs) incorporate essentially two and four separate synthesizers on a chip for precise control of the phase, frequency, and amplitude of multiple signals.

Direct-digital-synthesizer (DDS) technology allows a single source to precisely control signal frequency and phase with high-speed switching. But integrate multiple DDS devices on a single integrated circuit, and the capability expands to synchronized signal generation for a wide range of commercial and military applications. The new AD9958 dual-DDS and AD9959 quad-DDS devices offer such capability, with 32-b frequency tuning resolution, 10-b amplitude tuning resolution, and speeds to 500 MSamples/s.

These multichannel synthesizers support a broad range of applications requiring synchronous modulation, such as amplitude-shift keying (ASK), frequency-shift keying (FSK), phase-shift keying (PSK), linear sweep (amplitude, frequency, or phase), and can also be used for single-tone generation with dramatic savings in board space and costs per frequency. Applications requiring fast and precise changes of amplitude, frequency, and phase are perfect candidates for the AD9958/59.

Signal generation in a DDS starts with a 32-b phase accumulator, which is controlled by a frequency-tuning word (FTW) that is programmed by the user via the serial port. The FTW determines the step size of the counter, which controls the rate at which the phase accumulator overflows. This overflow rate is equal to the output frequency. At the heart of the operation is a proprietary digitally encoded phase-to-amplitude conversion algorithm. This algorithm operates with an instantaneous phase value from the counter and adds it to the 32-b phase angle from the previous clock cycle. It then truncates the phase information and converts it to a 10-b value that represents the amplitude of the sine wave. Lastly, a high-speed digital-to-analog converter (DAC) converts the amplitude information to the analog domain. Amplitude attenuation can be achieved by applying an output scalar in the digital domain, or by scaling the DAC's gain. The width of the phase accumulator (32 b) and the maximum system clock frequency combine to determine the maximum output frequency (Fo) that can be generated by the DDS, Fo= s)>/232, where 0 ≤ FTW ≤ 231 (limited by Shannon's theorem). Operating at a maximum system clock rate of 500 MSamples/s, the AD9959 produces output frequencies from DC to 250 MHz in steps of about 116 mHz.

In addition to lower cost per channel and reduced board space requirements, an inherent benefit of the AD99589/59 ICs is their ability to be precisely synchronized. Although synchronous, each channel has separate DDS cores and registers, and is thus completely autonomous. Phase offsets relative to each channel can be perfectly implemented for quadrature applications. This would be challenging to achieve in dual- and quad-channel applications using single-channel DDS ICs. The prime problem is usually the external delay between master and slave single-channel ICs. For applications requiring more than four channels, a more robust synchronization technique has been implemented in the AD9958/59 ICs. Another new feature allows synchronous loading of updated amplitude, frequency, and phase information for all channels.

The AD9958/59 ICs perform three main functions: direct modulation, linear sweep, and single tone generation. Each channel is independent and is programmed separately, but simultaneous operation can be limited for high levels of direct modulation due to the number of profile pins available. The part can be programmed for any combination of two-level direct modulation (also known as binary modulation), linear sweep, or single-tone generation without pin constraints. Simultaneous operation of four-, eight-, and sixteen-level modulation is restricted depending on the number of profile pins required. Amplitude, frequency, or phase can be modulated providing ASK, FSK, and PSK modulation. The resolution of the modulation is 32 b for frequency, 14 b for phase, and 10 b for amplitude. A ramp-up/ramp-down feature is provided. This allows the user to increment the decrement the amplitude before and after the modulated data sequence.

Linear sweep mode enables the AD9958/59 ICs to step amplitude, frequency, or phase precisely between two chosen points. This stepping is controlled by four user inputs; two for stepping from point A to point B, and two for stepping point B to point A. These two inputs (delta word and ramp rate) control the step size and the time between the steps. The resolution remains the same: 32 b for frequency, 14 b for phase, and 10-b for amplitude. The sweep function is pin controlled. Furthermore, the user may set the "no-dwell" bit to control the behavior of the DDS upon completion of the sweep. The DDS can be programmed to immediately return to the sweep start frequency or it can be allowed to dwell at the terminal frequency for a period of time.

The AD9958/59 ICs generate single tones to 200 MHz with a 500-MHz clock. This is slightly below the Nyquist criterion because harmonics mixed with the clock show up in band and are too close to be filtered. Figure 1 shows the wideband performance of the ICs due to the second and third harmonics versus the output frequency. Harmonically related spurious signals are typically below –60 dBc for output frequencies to 125 MHz and about –55 dBc for the rest of the band to 200 MHz.

Two concerns arising from the four-channel AD9959 were the coupling between adjacent DAC blocks and the presence of digital switching noise at one-quarter the system clock in the DAC spectrums. Either issue could reduce wideband and narrowband SFDR specifications if not addressed, creating unnecessary problems when frequency planning. The coupling issue is addressed with a combination of circuit, layout, and process techniques. Careful consideration for the placement of key signals and circuit blocks resulted in a multi-channel design that has very low interference from channel to channel. Figure 2 shows the adjacent-channel coupling performance under worst-case conditions (three channels set to the same aggressor frequency). Results are shown for one common DAC supply plane and four separate supply planes. Rigorous optimization and pin reduction, including several cases of combined supplies in critical sections of the DAC did not degrade their 10-b performance (Figs. 1 and 3). The digital section is now as much as four times the size of a single channel and uses the same number of supply and ground pins, but the digital switching noise is typically –75 dBc below the fundamental for all four channels.

The DAC implemented on the AD9959 was derived from an existing architecture, but was optimized for 10-b performance at 500 MSamples/s. Any area reduction in this block would be multiplied by the number of channels. Many common circuit blocks are shared between the channels as well to further reduce the die area. The clock input, band gap reference, and serial input/output (I/O) are all shared by the channels. The voltage reference was given special attention to minimize coupling and provide scalability between channels. The serial I/O was increased to 200 MHz operation and offers increased bit transfer.

The DDS ICs achieve low output phase noise. The output frequency is generated as a division of the reference frequency. The jitter accumulated on the sampling clock contributes most of the phase noise in the DDS. The division process occurring in the synthesizer reduces the sampling clock phase noise by a factor of approximately 20log(Fs/Fout). In Fig. 4, the lower noise spectral density plot shows that the residual phase noise measured at 100 kHz offset from a 181.5-MHz output frequency is approximately –154.5 dBc/Hz, reaching –157 dBc/Hz at offsets greater than 1 MHz. These plots represent AD9959 phase noise without accounting for reference clock noise, showing the contributions of the digital core and DAC. Summing the noise floor and normalizing to the Nyquist frequency (250 MHz), the total noise is measured to be approximately –62 dB, the noise floor associated with a 10-b DAC.

The upper noise spectral density plot shown in Fig. 4 demonstrates the phase noise performance after accounting for noise on the reference clock signal. The inclusion of the clock noise brings the total noise up significantly, showing the importance of maintaining a clean sampling clock when good phase-noise performance is necessary. Noise will drop as the output frequency decreases. At an output frequency of 100.3 MHz, the noise floor is –152.5 dBc/Hz offset 1 MHz and is limited by the clock jitter. Reducing the output frequency to 15.1 MHz brings the noise curve down to a floor of –162 dBc/ Hz.

Both ICs are supplied in 7 × 7-mm 56-lead LFCSP packages. In addition, an evaluation kit is available complete with operating software that boasts a powerful graphical user interface (GUI). The software runs on a PC, with a Universal Serial Bus (USB) connection to the evaluation board. P&A: $20.24 (AD9958) and $37.14 (AD9959)(1000 qty.); stock. Analog Devices, 804 Woburn St., Wilmington, MA 01887; (800) ANALOGD, FAX: (781) 937-1021, Internet:

For a block diagram of the AD9959 quad-DDS device, see Fig. 5.

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