FPGA Reconfigures Space-Based Systems

Oct. 7, 2010
The industrys first high-density, rad-hard reconfigurable field-programmable gate array offers an option to rad-hard ASICs in space applications.

Space is the final frontier, but it is a harsh one, requiring components capable of withstanding large levels of radiation. For complex processing in satellites and other spacebased systems, designers have been restricted to custom and expensive application-specific integrated circuits (ASICs). But the introduction of the off-the-shelf Virtex-5QV fieldprogrammable gate array (FPGA) from Xilinx provides a much-needed alternative to ASICs for deep-space applications. The new radiation-hardened FPGA is not only well suited for space, unlike an ASIC it is reconfigurable, allowing last-minute design changes and even modifications to critical systems after they have been launched.

The new Xilinx Virtex-5QV FPGA (Fig. 1) offers a unique combination of rad-hard processing power and reconfigurability. It is suitable for any environment in which radiation exposure may be an issue, including in low-earth-orbit satellites (LEOS) to systems supporting interplanetary missions. The radiation-hardened version of the firm's commercial Virtex-5 FPGA was developed under sponsorship by the United States Air Force, Air Force Research Laboratory (AFRL) at Kirtland Air Force Base (AFB), NM.

Built on a 65-nm silicon CMOS semiconductor process with copper conductors, the Virtex-5QV Space Grade FPGA provides rad-hard technology providing exceptional hardness to single-event-upset (SEU) events, total immunity to single-event-latchup (SEL) events, and data path protection from singleevent- transient (SET) events as well as extremely high tolerance to totalionizing- dose (TID) conditions.

The rad-hard features inherent in Virtex- 5QV devices are backed by the highest levels of in-beam testing by the Xilinx Radiation Test Consortium (XRTC) and equivalent to millions of device years in space radiation environments. As a result, Virtex-5QV FPGAs can be counted on to provide reliable protection against SEU instances, total immunity to SEL, high tolerance to TID, and data path protection from SET occurrences. The Virtex-5QV FPGA configuration memory, which controls all programmable aspects of the device, has been implemented with rad-hard dual-node latches that provide nearly 1000 times the SEU hardness of the standard cell latches in the commercial device. Additionally, the configuration latch is nearly impervious to upset by proton interaction.

The Virtex-5QV FPGA configuration control logic and JTAG controller have been hardened to SEU and SET with embedded triple module redundancy.

Each control register is implemented with independent and redundant error detection and correction circuits for autonomous state correction. This mitigation combination eliminates most single-event functional interrupts (SEFIs) and reduced orbital SEFI rates to approximately less than once every 10,000 years in a typical GEO environment.

Each configuration logic block (CLB) in the Virtex-5QV FPGA contains eight user registers. Each register is implemented with rad-hard, dual-node latches in a target-initiator configuration and thus provides the same protection from static SEU as with the configuration latches. Additionally, protection from SET during dynamic operation is provided by transient lters on the inputs of each register. The SET filters provide as much as 800 ps glitch filtration on the data, clock, clock enable, and set/reset input paths of each register.

The FPGA's digitally controlled impedance (DCI) logic controller is hardened to SEU and SET with embedded triple module redundancy. Each control register is implemented with independent and redundant error detection and correction (EDAC) circuits for autonomous state correction. This mitigation combination provides the first hardened DCI feature. In addition, the FPGA's block RAM contains an integrated embedded EDAC and writeback function to autonomously detect and correct SEU in block memory content. The writeback feature delivers high system reliability without the expense of additional support circuitry.

The space-ready FPGAs are based on the second-generation ASMBL column-based architecture of the Virtex-5 family with support in Xilinx's ISE Design Suite. Virtex-5QV devices integrate many of the same intellectualproperty (IP) system blocks, including flexible 36-kb/18-kb block randomaccess memory (RAM)/first-in, first-out (FIFO) memory blocks, second generation 25x18 DSP slices, poweroptimized high-speed serial transceiver blocks for enhanced serial connectivity, and PCI Express compliant integrated Endpoint blocks. Virtex-5QV devices contain generous processing capabilities, with 130,000 logic cells, 320 DSP Slices supporting xed and floating point operations, and 836 user input/output (I/O) connections programmable to more than 30 different standards for applications and ease of interfacing to a wide variety of systems and their components. The Virtex-5QV FPGAs include 18 channels of 3 Gb/s multigigabit serial transceivers for chip-tochip, board-to-board, and box-to-box communications.

According to Amit Dhir, Senior Director for Aerospace/Defense & High-Performance Computing Business at Xilinx, "For over 20 years Xilinx has been enabling space systems designs with our rad-tolerant FPGA platforms and Single Event Effects mitigation design methodologies. With the Virtex- 5QV FPGA we are enabling new and unprecedented applications in FPGAs, bringing to market a platform that utilizes new rad-hard by design technologies paramount in providing radiation hardness, higher density, higher levels of performance and simpler mitigation schemes compared to previous Xilinx devices."

Dr. David A. Hardy, Associate Director, Space Technology, Space Vehicles Directorate, AFRL, adds: "The radiation-hardened Xilinx Virtex-5 FPGA represents the biggest step ever taken in performance and affordability for space electronics. Our Air Force satellite developers will be able to do more on-board processing using less power than ever before. And, the flexibility of the Virtex-5QV FPGA means that satellite development schedules will be shortened, saving even more money."

The firm's space-grade devices, which also include Virtex-4QV radiationtolerant FPGAs, are unique in the industry because they are the only FPGAs with support for specified total ionizing dose (TID) and characterized single-event effects (SEE). They have been a part of numerous deep-space projects, including NASA's SpaceCube computer system (Fig. 2) on board the International Space Station (ISS) and even for interplanetary missions, such as on the Mars Rover.

In an example application, the radhard Virtex-5QV FPGA can be used for processing digital RF signals to and from an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) in a software-defined-radio (SDR) modem. The FPGA handles receive decoding and demodulation and transmit encoding and modulation as well as digital filtering and coordination of control interfaces (Fig. 3).

The Virtex-5QV FPGA is well suited to help next-generation space systems push the boundaries for performance and capability in applications such as video display, communications, radar, encryption, packet processing and control. Along with the rad-hard Virtex- 5QV FPGAs and the Virtex-4QV family of radiation-tolerant FPGAs, the firm also provides IP, ISE Design Suite development tools, kits and support as part of Targeted Design Platforms for delivering programmable solutions that help developers avoid the high cost of ASIC development without sacri cing performance. Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124; (408) 559- 7778, Internet: www.xilinx.com/esp/aeropace.htm.

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