SiGe Fires Single-Chip Fractional-N Synthesizer

Dec. 1, 2003
A high-frequency SiGe process, a carefully designed sigma-delta modulator, and high-frequency monolithic VCOs combine for a synthesizer capable of operating to 30 GHz.

Silicon-germanium (SiGe) semiconductor technology has long held the promise of high-frequency operation with high levels of integration. The process technology made headlines in the early 1990s with claims of device transition frequencies that could surpass expensive gallium-arsenide (GaAs) technology while using standard silicon wafers. While the technology is now making its way into a variety of integrated circuits (ICs), mainly for cellular handsets and wireless-local-area-network (WLAN) cards, its integration potential has been largely untapped. A single-chip fractional-N SiGe synthesizer from Centellax (Santa Rosa, CA), however, offers a glimpse of what this technology can achieve, using multiple varactor-tuned voltage oscillators to cover frequencies between 20 and 30 GHz and a total of more than 10,000 transistors on chip.

The company, launched in February 2002, was founded by some of the leading design engineers in the high-frequency industry: Dr. Julio Perdomo, Jerry Orr, Christian Bourde (all formerly of Agilent Technologies), and German Gutierrez, with a background that includes stints at Broadcom and Silicon Wave. The company has already established a reputation for innovative use of SiGe heterojunction-bipolar-transistor technology with a series of extremely broadband amplifier (nominally for optical communications networks) ICs and modules, signal-processing modules, and switch/attenuator ICs through 50 GHz. For example, the UAXX65XX family of monolithic-microwave-integrated-circuit (MMIC) amplifier ICs cover a bandwidth approaching 65 GHz, with frequency range from 0.04 to 65 GHz.

The latest development from Centellax is a fractional-N frequency synthesizer (Fig. 1) that takes advantage of the excellent high-frequency performance of SiGe as well as the potential for integration when using silicon CMOS processing. The fractional-N frequency synthesizer IC contains the entire phase-locked-loop (PLL) along with the digital fractional dithering functions (Fig. 2). The synthesizer features in-phase (I) and quadrature (Q) output ports and generates signals over the ranges of 10 to 15 GHz and 20 to 30 GHz. Its integration of VCO, synthesizer, and digital signal processing on a single chip offers a significant savings in size, cost, and power consumption compared to existing solutions for a wide range of broadband applications in commercial, industrial, and military systems.

A fractional-N synthesizer differs from a traditional integer-N in which the division ratio, N, is a fixed integer, forcing a trade-off between loop bandwidth (and tuning speed) and frequency step size. In a fractional-N synthesizer, the divide ratio is dynamically varied or dithered to achieve intermediate division ratios. In the Centellax device, dithering is accomplished by means of an all-digital delta-sigma modulator, allowing fine frequency resolution but with wide loop bandwidths. Although dithering the division ratio can introduce quantization noise, careful design of the modulator can achieve a similar lowpass transfer function as the reference source, in effect suppressing higher-frequency noise. By using a high-speed SiGe HBT process, Centellax can fabricate wideband monolithic voltage-controlled oscillators (VCOs) capable of fundamental frequencies of 30 GHz and higher as part of the fractional-N frequency synthesizer design.

Traditionally, HBT devices have been fabricated on GaAs or InP substrates, requiring complex and expensive process technologies. One of the benefits of SiGe HBT devices is that they can be fabricated with conventional silicon CMOS technology with only a few additional process steps. There are two heterojunctions in SiGe HBTs, one at the emitter-base junction and the other at the base-collector junction. SiGe technology allows cutoff frequencies of 300 GHz and more for small-geometry HBT devices, supported by all the benefits of traditional silicon CMOS integration of additional analog and digital structures. SiGe also features low 1/f device noise, high levels of analog and digital device integration, low materials costs, and low power consumption compared to other high-frequency semiconductor materials, such as InP and GaAs.

The new synthesizer features an integrated CMOS delta-sigma controller with optional external delta-sigma interface. The IC can generate fundamental frequencies to 30 GHz with step sizes as small as 25 kHz. It achieves typical output power of +5 dBm from its driver amplifier and includes divide-by-two outputs for half-frequency applications. The sigma-delta-modulator-based division-dithering approach minimizes phase noise (about 10 dB worse than the reference or typically −85 dBc/Hz offset 10 kHz from the carrier) while providing frequency-switching speeds (about 100 ns) associated with wide loop bandwidths.

The highly integrated Centellax fractional-N synthesizer IC requires minimal external components (external resistors and capacitors for the loop filter). Depending on these external circuit elements, the loop bandwidth can be extended to the tens of megahertz range to accommodate reference frequencies to 600 MHz while achieving aggressive suppression of VCO noise over wide bandwidths and also maintaining fast frequency switching speeds. The wide loop bandwidth also supports modern modulation formats, including wideband frequency modulation (FM) and frequency-shift-keying (FSK) modulation.

The fractional-N IC includes a bank of varactor-tuned VCOs, each one covering a subset of the desired frequency range. This allows a broad tuning range while maintaining low phase noise. In addition to the high frequency coverage, the VCO output can be selected through an on-chip divide-by-2 prescaler for half-rate applications. Quadrature output signals are also available, or can be disabled to conserve power.

The IC's fully programmable integer divider features division modulus ratios from 4 to 255. The divide ratios are dynamically switched according to the CMOS fractional dithering sequence. Dithering can be initiated with the on-chip selectable second- or third-order delta-sigma modulator, with optional least-significant-bit (LSB) dithering from a 31-b pseudorandom-bit-sequence (PRBS) generator, or externally by deselecting the on-chip modulator. The flexible fractional-N synthesizer IC also allows the use access to the divider input port, to disable the on-chip bank of VCOs and use an external VCO. Centellax, 451 Aviation Blvd., Suite 101, Santa Rosa, CA 95403-1069; (866) 522-6888, (707) 568-5900 ext. 46, FAX: (707) 568-7647, Internet:

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