Two-Chip IF Receiver Prepares For 3G Standards

April 12, 2007
This solution combines a dual-channel, variable-gain amplifier with 1-dB resolution at high IFs and a diversity receiver with a 150-MSamples/s, 14-b ADC.

As mobile handsets evolve to offer more multimedia content, the wireless infrastructure must be equipped to support higher-data-bandwidth devices. A two-chip intermediate-frequency (IF) receiver solution from Analog Devices (Norwood, MA) provides the performance needed for next-generation, multi-carrier wireless base stations to meet emerging third-generation (3G) cellular transmission standards. The solution comprises the dual-channel AD8376 variable gain amplifier (VGA) and AD6655 IF diversity-receiver solution.

Together, the AD8376 and AD6655 form a two-chip, dual-channel IF receiver that is optimized to simultaneously handle both the main and diversity receive paths (see figure). In a six-carrier TD-SCDMA application, for example, the IF receiver replaces 48 discrete components and promises to reduce power consumption and physical volume in micro- and pico-cell base stations.

The AD8376 is a digitally controlled VGA that enables 1-dB gain-step resolution over a 24-dB range at IFs to 600 MHz. The device offers output third-order intercept linearity of +50 dBm at 140 MHz. In addition, the AD8376 provides precise fine-gain-step adjustment for digital radio receivers.

The gain range is controlled by means of a five-pin digital interface. With a maximum transconductance of 67 mΩ–1,s, the AD8376 offers a signal gain of 20 dB when driving a 150-Ω load. When it is driving a 250-Ω differential load, the maximum signal gain rises to ~24 dB. This VGA promises to reduce current consumption by achieving its +50-dBm output third-order intercept with 130 mA quiescent current at +5 V.

For its part, the AD6655 IF diversity receiver integrates many of the functions required for the diversity receive path. For example, it includes an ultra-low-latency peak detector and a rootmean-square (RMS) power monitor that can be used with the AD8376 and logic to form a flexible AGC. In addition, the AD6655 includes a 14-b analog-to-digital converter (ADC) that operates at 150 MSamples/s followed by a digital downconverter (DDC).

The AD6655's DDC functionality includes a 32-b numerically controlled oscillator (NCO) as well as a decimating halfband filter and an output finite-impulse response (FIR) filter. Together, they provide an effective bandpass-filtering function while reducing the output rate. The result is a signal-to-noise ratio (SNR) of 75 dB at 70 MHz. The AD6655 is offered in both 12- (AD6653) and 14-b resolutions with sample rates of 80, 105, 125, and 150 MSamples/s.

Both the VGAs and IF diversity receivers are sampling with production scheduled for June. In 1000-piece quantities, pricing is $6.25 for the AD8376; $4.25 for the single-channel AD8375; and $57.97 and $97.50, respectively, for the 12-b and 14-b versions of the AD6653.

Analog Devices, Inc., 804 Woburn St., Wilmington, MA 01887; (781) 937-1989, FAX: (781) 937-1078, Internet:

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