Clock-Divider IC Has Delay Adjustment

Designed for outstanding phase-noise performance, model HMC988LP3E is a clock divider and delay management IC that can handle clock signals as high as 4 GHz, dividing them by ratios of 1, 2, 3, 4, 8, 16, or 32. The IC is ideal for sample clock phase alignment of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) and backplane clock skew management in communications and test systems. It provide fine and coarse modes of phase delay. The fine delay mode works for output frequencies to 1 GHz with 20-ps resolution in 60 steps. The fine delay adjustment, which works up to 1 GHz output frequencies, offers output phase control with 20 ps resolution in 60 steps. Additional timing functions include clock synchronization, clock invert, and clock slip options.The IC provides a standard differential LVPECL output and a flexible input which can be optimized for LVPECL, LVDS, CML, or CMOS signals. The phase-noise floor is -170 dBc/Hz with 80-ps rise/fall time. Up to eight of the devices can be used together on an SPI bus. The IC draws only 68 mA current from a +3.3-VDC supply (it can also operate from a +5-VDC supply if an optional on-chip regulator is used) and is housed in a 3 x 3 mm QFN surface-mount package. Hittite Microwave Corp., 2 Elizabeth Dr., Chelmsford, MA 01824; (978) 250-3343, FAX: (978) 250-3373, e-mail: [email protected], www.hittite.com.