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Boosting Power with Silicon CMOS

Jan. 6, 2017
Several IC design approaches, including stacking transistor cells, can be applied for higher-power Si CMOS PAs at microwave frequencies.

Silicon CMOS semiconductor technology has been the basis for a wide range of analog, digital, and mixed-signal semiconductor devices. Traditionally, though, it does not fare well in high-frequency amplification applications. A different semiconductor technology, such as gallium arsenide (GaAs), is typically recruited to raise the amplitude of high-frequency signals.

In hopes of gaining more power at higher frequencies from Si CMOS, Jie Cui from the School of Electrical and Optical Engineering, Nanjing University of Science and Technology (Nanjing, China) and Purdue University (West Lafayette, Ind.), working with Sultan Helmi, Yingheng Tang, and Saeed Mohammadi from Purdue Univ., reviewed a great deal of the work already performed on increasing the operating frequencies of Si CMOS processes. In concert, they stacked on-chip transistors in different configurations to achieve higher levels of output power.

The team reviewed the performance levels of a number of different stacked CMOS PAs, operating from RF through millimeter-wave frequencies, including a number of PAs developed at Purdue. As with other researchers, they discovered that various limitations in Si CMOS must first be overcome for higher performance. For example, output power is limited by the low breakdown voltages of CMOS. In addition, limitations in frequency, efficiency, and bandwidth are caused by the parasitic elements of active and passive components in CMOS technology, including on-chip passive components with high loss (e.g., inductors, transformers, and transmission lines).

Some of the parasitic limitations can be overcome by using a substrate material with high thermal conductivity, such as aluminum nitride (AlN), in place of the standard Si-based substrates. In addition, the use of an enhanced silicon-on-sapphire (SOS) CMOS process can also minimize parasitic elements when fabricating PA circuitry for improved higher-frequency performance.

Employing an innovative interconnection scheme, the three transistors of a triple-cascode cell were fabricated and stacked using a combined layout cell with low parasitic elements. The researchers were able to achieve power outputs at frequencies approaching the performance levels of commercial GaAs PAs.

One of the designs features a stacked transistor configuration and switchable input matching network for optimizing wideband performance by dividing the total bandwidth into two portions. When the input matching switch is in the “on” state, the PA covers a bandwidth of 1.8 to 2.4 GHz; when the switch is in the “off” state, the PA operates across a bandwidth of 2.4 to 3.4 GHz. This particular design provides 6-dB gain with better than +13 dBm output power at 1-dB compression (P1dB) with better than 13% peak power-added efficiency (PAE). Fabricated with a 0.25-µm SOS CMOS process, it is a good example of the higher-frequency PA performance achievable with Si CMOS.

See “Stacking the Deck for Efficiency,” IEEE Microwave Magazine, Vol. 17, No. 12, December 2016, p. 55.

About the Author

Jack Browne | Technical Contributor

Jack Browne, Technical Contributor, has worked in technical publishing for over 30 years. He managed the content and production of three technical journals while at the American Institute of Physics, including Medical Physics and the Journal of Vacuum Science & Technology. He has been a Publisher and Editor for Penton Media, started the firm’s Wireless Symposium & Exhibition trade show in 1993, and currently serves as Technical Contributor for that company's Microwaves & RF magazine. Browne, who holds a BS in Mathematics from City College of New York and BA degrees in English and Philosophy from Fordham University, is a member of the IEEE.

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