Working Graphene With Silicon CMOS

Nov. 26, 2013

Researchers are pursuing ways in which emerging graphene devices can be integrated with silicon CMOS circuits.

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Work on graphene at Columbia University has included work by engineering Ph.D. candidates Michael Lekas and Sunwoo Lee, who were awarded a Qualcomm Innovation Fellowship (QinF) and associated $100,000 funding for their work on nanoelectromechanical systems (NEMS) designed to be compatible with silicon CMOS devices for next-generation high-frequency circuit designs. Their work is aimed at making multiple wireless functions more achieveable and affordable within single products, such as handheld communications devices. The researchers have worked with the university’s Mechanical Engineering Associate Professor James Hone and Electrical Engineering Professor Ken Shephard in attempting to develop graphene solutions that are compatible with existing silicon chip technology. To learn more, click here.

About the Author

Jack Browne | Technical Contributor

Jack Browne, Technical Contributor, has worked in technical publishing for over 30 years. He managed the content and production of three technical journals while at the American Institute of Physics, including Medical Physics and the Journal of Vacuum Science & Technology. He has been a Publisher and Editor for Penton Media, started the firm’s Wireless Symposium & Exhibition trade show in 1993, and currently serves as Technical Contributor for that company's Microwaves & RF magazine. Browne, who holds a BS in Mathematics from City College of New York and BA degrees in English and Philosophy from Fordham University, is a member of the IEEE.