Viewpoint: Power Displaces Timing As Top IC Design Challenge?

Of all the problems confronting chip designers, power is quickly becoming Enemy Number One. Speaking at last year's ISSCC, Intel chief technology officer, Pat Gelsinger, called power consumption "the key concern for microprocessor technology."

Advanced processes and increased clock frequencies are making IC power requirements untenable: Today, 100 watts per square centimeter is the norm for processor applications and extremely high-density DSPs. Intel's Itanium and Apple's G4 processor have a power density in this range: The G4, for example, consumes 134 watts in a 1.2 cm2 die size.

Circuits with very high power consumption exhibit significant thermal gradients across the chip. This is problematic because conventional timing analysis assumes a single temperature for the entire device, even though it is well known that timing is temperature dependent. The usual response is simply to minimize overall chip temperature through the use of more sophisticated, and expensive, packaging.

But the problem is even more convoluted: For all the history of MOS, designers have learned that as temperature goes up the circuit slows down. This is because electron-hole mobility-a key factor for currents-decreases with increasing temperature. However, in nanometer design, at low voltages, transistors can speed up at high temperatures. This effect has significant implications for the design flow. It demands that a designer know the temperature of the circuits to design it correctly.

Today's multi-million transistor IC consumes large amounts of power, generating heat and unwanted design effects. At the same time, portable gadgets of all types demand that batteries live as long a life as possible. So whether using too much or too little power is the issue, managing it is quickly overtaking timing as the top design challenge. Reducing supply voltages while boosting clock speeds into the gigahertz range pushes thermal densities off the charts. Managing these issues simultaneously calls for the creation of a power signoff standard for nanometer-scale chips.

Power signoff verifies that power and current specs are accurate, and that delay and noise impacts caused by power are accounted for and fixed. For example, once the time-averaged power has been calculated, its values can be used to determine junction temperatures and thermal gradients, and these instance-specific junction temperatures can be used to more accurately calculate delays. These same temperature values can also be used to more accurately evaluate reliability parameters such as electro-migration limits since they, like delay effects, are highly sensitive to temperature.

New design tools must model complex electrical effects based on the interactions of resistance, capacitance, and inductance, while analyzing designs in their entirety since the effects caused by power are interdependent throughout the power grid.

While power management to control the negative impact of electrical effects is happening, power consumption specifications are also becoming critical. For example, the fewer times the circuit switches, then the smaller the capacitive load, and the lower the power supply voltage. This translates directly to lower power consumption. As the process technology continues to evolve, with sub-100nm designs being started today, the power supply voltages are dropping. However, the complexity of today's designs (i.e., switched capacitive load, C), as well as increasing clock frequencies (f) lead to an overall power increase.

A good power-saving design methodology must address all components of power dissipation throughout the design process. Indeed, while a low-power design is the ultimate goal, management and control of power consumption must become an integral part of the design flow.

How can power reductions be accomplished? Following RTL synthesis, design optimization includes steps such as power gating - limiting power in different areas to reduce leakage currents. This permits the power grid to be completed prior to layout using a correct by construction approach rather than the ad hoc approach used today. Next, the designer produces a placement which provides first-order timing data-an initial indication of delay that will occur in the interconnect of the design. During post-placement optimization the designer can reduce power by using techniques such as "high threshold cells," placed in areas where timing is not critical. They do not alter the timing of critical paths but reduce >eakage in non-critical paths.

Clock trees - monster power users - are next for power reduction techniques. Clock gating turns the clock off when a circuit is inactive, another scheme optimizes the tree itself by providing selected flip flops with unbuffered clock inputs to save on clock power, a technique that impacts placement and routing. However, in a placement-controlled environment such as this, the technique can be managed effectively to reduce power significantly in the clock tree. For most ASICs, clock trees are done automatically, while for large, complex chips some manual adjustments are necessary.

Routing completes the process, followed by final verification and fine tuning. At this point thermal gradients and IR drop data are calculated. With this information the designer can determine if the circuit meets timing, power, thermal and noise specifications prior to completing the power signoff.

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