Digital Receiver Processes 3 GHz

This compact but powerful DSP-based receiver digitizes input signals over a 3-GHz bandwidth with 1-b resolution and sampling rates to 2 GSamples/s.

Digital receivers offer versatility that is simply not possible with conventional superheterodyne or homodyne analog receivers. The model RX00103-005 digital receiver from LNX Corp. (Salem, NH) is a case in point: the wideband, dual-channel module can capture the most transient signals from DC to 3 GHz at sampling rates to 2 GSamples/s. It makes the analog-to-digital conversion with 10-b resolution, providing 7.4 effective bits at a sampling rate of 1.4 GSamples/s for a spurious-free dynamic range of 58 dB with a 700-MHz input signal. Equipped with generous digital-signal-processing (DSP) capabilities, the compact receiver is ideal for commercial applications in the software-defined radios (SDRs) of cellular base stations and other communications systems as well as in military radar and electronic-warfare (EW) systems.

The model RX00103-005 digital receiver (see figure) is a single printed-circuit board (PCB) with RS-232C, VME, and HOTlink™ interfaces. The board features a pair of model TS83102 (10-b, 2-GSamples/s) analog-to-digital converters (ADCs) from Atmel Corp. (San Jose, CA), and as many as three Virtex-II field-programmable gate arrays (FPGAs). The ADCs work with a companion model TS81102 demultiplexer, which processes the 10-b ECL output signals from the ADCs onto an 80-b, single-ended bus running at one-eighth the sampling rate. The sampling delay and gain of the ADCs can be adjusted to support synchronizing and interleaving of multiple receiver boards for higher sampling rates.

The demultiplexer's output is connected to a Virtex-II FPGA using an 80-b single-ended data bus and a differential clock. Each FPGA incorporated into a given receiver has a CPU bus for direct communication with an on-board CPU module. The CPU provides the user interface, local control, and FPGA configuration for the receiver, as well as the RS-232C interface. The receiver includes 32 MB of flash memory to store FPGA configuration and other command information. Data collection and processing is controlled by means of a simple command set.

The receiver's high-speed Hotlink interface is implemented by means of a model CYP15G0101DXA high-speed-optical-transceiver link (HOTlink II™) from Cypress Semiconductor Corp. (San Jose, CA), which supports data rates of 0.2 to 1.5 GSamples/s. The transceiver contains all the logic needed for the serialize/deserialize (SERDES) function as well as clock recovery. One of the FPGAs serves as the system host to the transceiver, with data written/read between the transceiver and FPGA with the aid of a dual-port memory bank within the FPGA. The memory bank is also accessible by the CPU.

The RX00103-005 digital receiver can be powered by means of a 10-pin terminal block (for bench-top operation) or the VME backplane. Typical requirements are 700 mA at +3.3 VDC, 250 mA at +5 VDC, 1.8 A at ­5 VDC, 300 mA at +1.5VDC, and 2.5 A at +2.5 VDC. The company offers both standard and custom signal-processing algorithms for the receiver.

The ISO 9001:2000 certified company also offers 38-GHz (37 to 40 GHz) transmitters and receivers for wideband line-of-sight applications. The transmitters and receivers, which operate with local oscillators (LOs) from 8 to 13 GHz and 2-GHz intermediate frequency (IF), are supplied with WR-28 waveguide RF inputs and SMA LO and IF connectors. The transmitter measures 7.1 × 3.0 × 1.0 in. while the receiver measures just 4.99 × 1.4 × 0.075 in. LNX, 8B Industrial Way, Salem, NH 03079; (603) 898-6800, e-mail: [email protected], Internet:

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