Working Graphene With Silicon CMOS

Working Graphene With Silicon CMOS

Researchers are pursuing ways in which emerging graphene devices can be integrated with silicon CMOS circuits.

Download this article in .PDF format
This file type includes high resolution graphics and schematics when applicable.

Work on graphene at Columbia University has included work by engineering Ph.D. candidates Michael Lekas and Sunwoo Lee, who were awarded a Qualcomm Innovation Fellowship (QinF) and associated $100,000 funding for their work on nanoelectromechanical systems (NEMS) designed to be compatible with silicon CMOS devices for next-generation high-frequency circuit designs. Their work is aimed at making multiple wireless functions more achieveable and affordable within single products, such as handheld communications devices. The researchers have worked with the university’s Mechanical Engineering Associate Professor James Hone and Electrical Engineering Professor Ken Shephard in attempting to develop graphene solutions that are compatible with existing silicon chip technology. To learn more, click here.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.