Form GaAs/InGaAs Lasers On Virtual Ge

Oct. 22, 2009
GaAs/InGaAs quantum-well lasers can be formed on virtual Ge substrates on silicon by means of metal-organic-chemical vapor deposition using several growth techniques.

Reliable GaAs-based optoelectronic devices, such as GaAs/InGaAs quantum well lasers, can be realized on silicon substrates using several advanced techniques. Fabrication involves first forming germanium (Ge) stripes on a silicon dioxide (SiO2) trench-patterned silicon substrate via aspect ratio trapping (ART), where any defects originating from the Ge/Si interface are trapped by laterally confining sidewalls. Defects arising from above the SiO2 film are reduced by means of an optimized epitaxial lateral overgrowth (ELO) process followed by chemical mechanical polishing (CMP) to provide a planar Ge surface. Then, a GaAs/InGaAs laser structure is overgrown on the virtual Ge substrate. This new fabrication method overcomes traditional problems plaguing GaAs/Ge integration, including Ge autodoping and antiphase domain defects in GaAs.

In recent decades, much effort has been made to fabricate electronic and optical devices on GaAs/Si.1-6 However, major problems remain unresolved, in particular, the high density of threading dislocations in GaAs layers grown directly on Si due to the 4-percent lattice mismatch and the difference in the coefficient of thermal expansion (CTE) between the two materials. The threading dislocations act as nonradiative recombination centers in optical devices and lead to device performance degradation. To date, significant progress has been made in reducing GaAs dislocation density for material growth by employing various epitaxial schemes such as cycle thermal annealing,4 epitaxial lateral overgrowth,5 and growth on compositionally graded SiGe buffers.6 However, these methods generally require relatively thick epitaxial layers and/or high-temperature annealing steps, which may complicate integration with Si-based integrated circuit technologies.

Ge is an ideal intermediary material between GaAs and Si because of its complete miscibility with Si and its close lattice match with GaAs at room temperature.7 Recently, the current researchers demonstrated low-defect Ge and GaAs materials grown in SiO2 trenches on Si via the ART method,8,9 where threading dislocations arising from lattice mismatch are trapped at vertical sidewalls confining the growth region. Full trapping of dislocations has been demonstrated for trenches to 400 nm in width without the formation of additional defects at the sidewalls above 250 nm initial growth. Although misfit dislocations are fundamentally unavoidable, they may be inconsequential to device performance if they can be trapped within a thin layer near the Ge/Si or GaAs/ Si interfaces, away from the device active region. In fact, ART-based high-performance Esaki diodes10 and MOSFET11 devices using monolithically grown GaAs/ Ge/Si structures have been successfully demonstrated.

This article reports on 980-nm GaAs/In- GaAs lasers grown on virtual Ge substrates, for which the Ge thin film was grown on Si (001) substrates via the ART method followed by CMP. The laser diodes are uncoated edge-emitting broad-area devices. Despite the fact that unoptimized laser structures have relatively high series resistance and large threshold current densities, this ART-based approach provides a promising pathway with several unique features in achieving high-performance III-V devices on Si. The approach allows misfit-defectinduced threading dislocations in Ge to be essentially trapped within a limited layer thickness inside SiO2 trenches via ART.8 The density of coalescence defects, which have been seen to be the major cause during coalesced growth,12 can be dramatically reduced by enhancing ELO, through which large-area, low-defect Ge can be obtained. GaAs overgrowth on the polished planar Ge surface enables further reduction of threading defects with buffer layer optimization at GaAs/ Ge interface. On-axis Si (001)-based virtual Ge substrates created by the ART + ELO growth process possess off-cut surface characteristics, which lead to antiphase domain (APD) reduction in overgrown GaAs.

The substrates used in this study were 200-mm-diameter ptype on-axis Si (001). A thin SiO2 layer was thermally grown on the Si substrate, followed by conventional photolithography and reactive ion etching (RIE) techniques to form multiple sections of trenches and waffle patterns, exposing the Si surface along the direction. Each section has a 0.25-m trench width. The SiO2 spacer between neighboring trenches varies from 0.25 to 20 m in the various trench sections, while sections were separated by 10 m of SiO2. After wafer preparation and prior to growth, the final trench height was about 480 nm.

Two-step low-pressure MOCVD processes were performed in this study. First, an epitaxial Ge layer was grown on the patterned substrate under optimized growth conditions similar to that described previously.8 Ge growth was terminated after the Ge layer slightly coalesces in the 20- m spacer section (later referred to as the ELO section), which corresponds to an average layer thickness of about 4 m. Then, a CMP process was used for planarization of the Ge-SiO2 composite structure.13 Before GaAs overgrowth, the polished Ge/Si substrate was cleaned with successive dips in H2O2 solution and 1:50 diluted hydrofluoric (HF) acid, with deionized water rinses between steps. In the second growth step, GaAs layers were deposited in a separate MOCVD reactor at constant low pressure (70 Torr) by using triethylgallium (TEG) and arsine (AsH3) for buffer layer growth and trimethylgallium (TMG), trimethylaluminum (TMA), trimethylindium (TMI), and AsH3 for upper structural layer growth. Prior to buffer layer growth, the wafer was baked at +600C for 10 minutes under H2 overpressure followed by 2 minutes of As-coating by introducing AsH3 overpressure. Then the growth temperature was reduced to +400C for 30-nm GaAs buffer layer growth followed by a three-period GaAs (10 nm)/Al0.4Ga0.6As (15 nm) superlattice structure grown at +600C. Finally, an n-type GaAs base layer and 980 nm GaAs/InGaAs laser structure were grown using various growth temperatures. The laser structural growth rates were kept at 7 nm/min for the buffer layer and 50 nm/min for the top layers. Carbon tetrabromide and SiH3 were used for p- and n-type doping, respectively. Each growth run contained both a GaAs (001) substrate and Ge (001) substrate, in addition to the Ge ART virtual substrate, for comparison.

The virtual Ge ART substrate was examined by optical Nomarski microscopy before GaAs overgrowth. These post-CMP wafers showed smooth surface morphology in all sections except the ELO trench section, in which linear depressions existed due to incomplete coalescence of the Ge film over the oxide spacer. After GaAs overgrowth, the surface looked very smooth in the scanning electron microscope (SEM) on all sections except the ELO section, which retained the pregrowth Ge surface feature. Cross-sectional SEM images of the laser structure are shown in Fig. 1. Figure 1(a) was taken from a trench-patterned section with 10-m SiO2 spacer while Fig. 1(b) was from the ELO section. In Fig. 1(c), the top-view SEM of the ELO section indicated that the overgrown film coalesced with a variable facet, suggesting that the linear depression must be removed or electrically isolated for laser device fabrication.

Room-temperature photoluminescence (PL) mapping was conducted for lasers grown on multisection virtual Ge ART substrate using a 514-nm argon (Ar) laser for optical excitation at 30 mW output power. Since the GaAs cap layer has strong absorption of the laser line, the GaAs cap layer was etched off under identical etching conditions, for all inspected samples, before PL measurements. Mapping results showed that the ELO section demonstrated the best PL characteristics of all the patterned sections, which confirmed the results obtained from etch pit density (EPD) analysis on virtual Ge ART substrates, from which the lowest etch pit density has been demonstrated from ELO regions.14 In Fig. 2, single PL spectrum results measured from the 1-m spacer section and ELO section are compared to those grown on GaAs and Ge substrates. All samples were grown under the same conditions. The figure shows that the PL peak intensity measured from the ELO section is about 60 percent that on a GaAs substrate, but is three times higher than that on the 1-m spacer section, as well as about five times higher than that on a Ge (001) substrate. This implies that the material quality varies depending on the initial ART mask pattern with which the Ge layer was grown. Although the uncoalesced ELO section demonstrated the best epitaxial quality by PL, the laser diodes were fabricated and tested from the fully coalesced 1-m spacer section because its planar surface allowed more straightforward laser device fabrication.

The key step for achieving highperformance lasers on a Ge substrate is the growth of a low-defect GaAs transitional base layer, which is designed as a lateral n-type conduction layer for laser diodes. Without deliberate growth optimization, issues related to antiphase domain (APD) and Ge contamination in GaAs may severely degrade or even destroy the overgrown device performance.15-19

In this case, because the Ge film was grown on exact (001)-oriented Si substrates, APDs become a primary concern due to the well-recognized polarity mismatch (polar/non-polar) at the GaAs/Ge interface. Fortunately, growth calibration revealed that the tendency of APD formation on a virtual Ge ART substrate surface is different from that observed on a Ge (001) substrate. The current researchers found that APDs can be effectively avoided using an optimized GaAs/AlGaAs superlattice structure for growing GaAs on virtual Ge ART substrates. As seen in Fig. 3(a), the high-density antiphase disordered networks appeared as expected in the 2-m GaAs base layer grown on an on-axis Ge (001) substrate. However, the same base layer grown on the virtual Ge ART substrate is nearly free of APDs as shown in Fig. 3(b). This can be attributed to APD reduction to the crystallographic growth behavior of the Ge grown on Si via ART.20

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Additional investigation into overgrowth on the virtual Ge ART substrate indicated that the density of APDs in GaAs layers decreases as the thickness of the polished Ge decreases. In other words, a thinner planarized Ge layer over the SiO2 spacer leads to higher GaAs quality, which is also a desirable aspect in improving heat transfer of overgrown devices on Si. Further experimental investigations are currently under way.

Ge autodoping has long been recognized as a potential problem for growing GaAs films on Ge substrates. 18,19 In this work, the optimal Ge growth temperature is +600C, which is lower than the growth temperature for GaAs-based laser diodes (about +680C). To avoid Ge film decomposition and possible contamination to the growth environment, the GaAs base layer is grown at +600C, +630C, and +680C after growing the GaAs/AlGaAs superlattice at +600C. During the base layer growth, the Si doping level is deliberately increased at each temperature step to the maximum value that yields good surface morphology at that temperature. This incremental increase of growth temperature and Si doping has been proven to successfully suppress Ge vaporphase contamination and maintain superior base-layer surface morphology. The laser structure and quantumwell structures were grown on top of this base layer. In Fig. 4, secondary ion mass spectrometry (SIMS) shows the epitaxial layer and doping profiles of the simple graded index separate confinement heterostructure (GRINSCH) laser structure. The Ge background doping was controlled below the detectable level in the laser structure, and its negative influence on laser performance can be neglected.

Transmission electron microscopy (TEM) was used to characterize the defect structure of the laser material on Si (Fig. 5). For optimized Ge/ Si growth, very few stacking faults or microtwins were observed near the boundary of the SiO2 mask, although voids were observed in the Ge layer at the coalesced region above SiO2 surfaces. The EPD result of the coalesced Ge layer in similarly patterned sections (with 1-m spacer) is in the mid 107 cm-2 region after CMP. In this work, the defect density of the active layer of the laser structure is believed to be in the level of low 106 cm-2 or high 105 cm-2, because the optimized overgrowth steps, such as buffer layer, super lattice structure and step-ramped temperature process result in further defect annihilation and re-direction at the GaAs/Ge interface.

The lasers grown for these experiments were simple gain guided broadarea edge-emitting structures fabricated from the 1-m spacer section. Figure 6 shows a schematic cross section of the laser stripe geometry. Laser stripes (20 m) were formed along the direction by wet etching into the pcladding layer; 20-m wide n-contact channels were formed by further wet etching into the n-GaAs base layer, evaporating Ni/Ge/Au/Ni/Au contacts and annealing. The distance from the edge of the contact to the edge of the ridge is 10 m. A 200-nm-thick nitride was used as the electrical isolation layer. Ti/Pt/Au was evaporated for the p-ohmic contact as well as the probe contact pads. After lapping the substrates to about 100 m thickness, laser bars were cleaved, forming laser facets along the direction. The cavity length of the tested laser diodes is 390 m in this study.

To quickly and effectively analyze the quality of the laser material grown on virtual Ge ART substrates, laser diodes were probed on unmounted bars under pulsed conditions at room temperature (with 1 s current pulses at a repetition rate of 1000 Hz). The forward laser turn-on voltage is about 1.5 V and the threshold current is about 240 mA, corresponding to threshold current density of 3 kA/cm2. These values are comparable to reported results.6,21-23 Without facet coating, peak power to 12 mW per facet and differential quantum efficiency of 22 percent were obtained.

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