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EDA Tools Speed Design Of RFICs

VeloceRF is an efficient RF modeling tool that enables the design of first-pass RF integrated circuits (RFICs) and system-on-chip (SoC) devices. Launched by Helic S. A. (Athens, Greece), the EDA tool is based on an efficient modeler that supports complete extraction of passive circuit elements, such as resistors, capacitors, and inductors, and allows inductor synthesis inside the normal design flow. It supports whole-chip modeling of RFICs without reliance on precharacterized inductor models, making it possible to rapidly customize a chip and optimize RF performance.

The software-modeling tool is the outcome of many years of research and silicon validation. It contains about 3000 inductive structures and several RF circuits that have been validated by Helic with more than 10 different silicon foundry processes. The software also includes a comprehensive line of test cases that have been developed in record times, including passive CMOS mixers, power amplifiers for cellular and wireless-local-area-network (WLAN) applications, voltage-controlled oscillators for GSM systems, and silicon-germanium (SiGe) BiCMOS low-noise amplifiers (LNAs). The software tool seamlessly interfaces with third-party schematic-capture and layout-editing tools. Through an automated layout synthesis feature called the Spiral Wizard, VeloceRF can generate constraint-driven layouts for all types of spiral inductors (square, rectangular, etc.) and even multi-inductor structures. The software is currently available as a module within the Virtuoso platform from Cadence Design Systems (San Jose, CA) and is compatible with both Sun/Solaris and Linux operating systems.

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