RF Design Environment Closes Verification Gap

Nov. 1, 2003
When integrated with industry-standard IC schematic and layout tools, this powerful suite of RF design and verification programs can improve the efficiency of the integrated-circuit design process.

Design verification requires a full suite of circuit and device models, analysis tools, and simulated measurement capabilities. The RF Design Environment (RFDE), introduced in September 2002 as the first product developed as part of the alliance between Agilent Technologies (Santa Rosa, CA) and Cadence Design Systems (San Jose, CA), brought frequency-domain circuit simulation technology to mainstream silicon RF/analog/mixed-signal designers. Using tools long familiar to microwave designers, including harmonic-balance and circuit-envelope simulators, these silicon integrated-circuit (IC designers) were brought one step closer to true verification within the Cadence IC design flow. Now, with the release of RFDE 2003C, the second product from that alliance, the gap between RF circuit/system design and verification closed even further in two key areas: system-level verification of RF circuit performance to wireless standards, and physical-level modeling of high-frequency components and interconnects in the layout of an RF IC.

With RFDE 2003C, wireless IC designers can now directly verify Cadence-based RF circuit schematics with modulated sources and measurements and pre-configured wireless test benches (WTB) based on current wireless standard specifications. Also, Cadence users can now generate accurate electromagnetic (EM) based models of passive on-chip components and interconnects using Momentum, a 2.5D method-of-moments-based simulation technology. These EM-based models are then simulated directly in the Cadence circuit schematic without the usual conversion to approximate lumped-element models, providing much greater accuracy for wireless and high-speed wire-line applications.

Traditionally, RF and microwave designers were concerned with frequency-domain data such as S-parameters, power gain, output power at 1-dB compression (P1dB), noise figure, third-order intercept point (IP3), and VSWR, and were comfortable designing single function blocks with frequency-domain simulation tools. Analog/mixed-signal designers, on the other hand, were accustomed to using SPICE for data such as voltage gain, AC sweeps of voltage gain and impedance, and noise voltage. However, because of the need to meet tighter time-to-market schedules, modern analog/mixed-signal IC designers need these simulators in one environment. To perform a full design and analysis, frequency-domain simulation is a vital complement to time-domain simulation. The RFDE 2003C environment provides frequency-based simulators from within the industry-standard Cadence design environment.

Harmonic Balance (HB) is a nonlinear frequency-domain simulator that rapidly analyzes multiple independent signals, no matter how closely spaced in frequency. Amplifier compression, harmonic distortion, oscillator spurious effects, phase noise, and mixer inter-modulation products are some of the analyses that HB is especially well suited for. The HB simulator from Agilent is a stable and robust technology that has benefited from continuous enhancements, making it the ideal analysis tool for large and highly nonlinear RF ICs. Enhancements include access to two different solvers (Direct and Krylov), three advanced pre-conditioners, memory waveform reduction techniques, and other advanced techniques (such as transient-assisted Harmonic Balance) for solving highly nonlinear circuits with digital content. Because it is a frequency-domain technique, distributed models are easily and accurately included. The HB simulator is most suitable for circuits with two or more large signal tones (multiple tones, frequency translation, mixers, detectors, multipliers). Frequencies need not be coperiodic. It is also well suited for high-Q circuits, dispersive circuits, ideal delays, transmission lines, microstrip lines, and N-port networks.

For example, Fig. 1 shows a two-tone simulation on a mixer with 960-MHz local-oscillator (LO) frequency and 20-kHz separation of two tones centered at 1 MHz and swept from 1 to 20 MHz while maintaining the 20-kHz separation. Simulation outputs were extracted in less than 2 min. Output data includes output spectrum, conversion gain, and second and third-order intermodulation distortion (IMD). The same simulation would take at least 1000 times longer using a time-domain SPICE-type simulator.

In highly nonlinear analog and RF circuits that might include flip-flops, switching devices, and frequency dividers, the HB simulator employs an advanced technique called transient-assisted HB (TaHB) to obtain a solution. First, a short transient simulation is run until a steady state output is reached. The solution is then transformed to the frequency domain and used as an initial guess for the HB simulator to converge into the final solution. In this case, output data include waveform, spectrum, and phase-noise plots, not available from just a time-domain simulation.

The Circuit Envelope (CE) simulator is a mixed-domain simulator that efficiently analyses pseudorandom, digitally modulated signals found in modern wireless circuits. It samples the modulation envelope (amplitude and phase, or I and Q) of the carrier in the time domain and then calculates the discrete spectrum of the carrier and its harmonics for each envelope time sample. The main advantage of its mixed-frequency/time-domain approach is that it performs the simulation only in the relatively narrow frequency band that is occupied by the modulated signal. Unlike SPICE, it does not need to analyze the complete spectrum up to the maximum frequency set by the simulation period, resulting in enormous savings of calculation time (Fig. 2).

The Circuit Envelope simulation output is a time-varying spectrum from which useful information, such as PLL frequency versus time data, adjacent-channel power ratio (ACPR), error vector magnitude (EVM), and noise power ratio (NPR) can be derived. Simulations can be performed on any user-specified orders of harmonics (5th, 7th, 9th, etc.), and all analyses can be carried out down to the transistor level. This simulator is well suited for analyzing I/Q modulators for such characteristics as modulation accuracy, frequency response, undesired leakage, IMD terms, efficiency, output power, modulator amplitude and phase accuracy, and EVM. Many of these analyses and simulations would be almost impossible to complete with a purely time-domain simulator such as SPICE. Other Circuit Envelope applications include pulsed signals, harmonic behavior during transient time, pseudorandom digitally modulated RF solutions, ACPR, EVM, and PAE simulation and optimization. The Circuit Envelope simulator can also handle a wide range of transient RF solutions, including PLL frequency versus time analysis (PLL lock time), analysis of automatic-gain-control (AGC) circuitry, PLL transient response (ringing, settling, and overshoot) simulation and optimization, and higher-order (5th, 7th, and 9th order) mixer intermodulation product analysis.

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The Convolution simulator is an advanced time-domain simulator that extends the capability of traditional transient analysis by accurately simulating dispersive, frequency-dependent components such as transmission lines and S-parameters. Convolution is best applied to baseband transient signals in the presence of distributed elements or frequency-domain models (dispersive circuits, ideal delays, transmission lines, microstrip lines, and N-port networks). Because both HB and CE results are in the spectral frequency domain, it is fast and easy for both simulators to process these spectral components and effectively optimize key results such as distortion and spurious signals (−1 dB compression, IP3, ACPR). Time-domain simulators are better suited to optimization of time-domain quantities.

Traditional RF tests rely only on discrete-tone figures of merit such as 1-dB compression point, third-order intercept, and group delay. Unfortunately, these metrics are not adequate for design and verification of complex modern wireless standards. The RF designer must ensure that the design performs according to modulated measurements such as EVM, ACPR, and BER, as defined by a given standard. These standards are based on waveforms with a unique modulation and framing structure. The same standards require that designs be tested based on burst structure with pilot, idle, and active portions, and with measurements specific to a portion or on the composite waveform. Often these measurements require meeting specifications for different data rates and sometimes need resolution at the bit level, requiring fully compliant parameterized sources and measurements.

RFDE 2003C addresses this need with a collection of preconfigured test benches for testing a complete circuit design, as well as wireless sources and measurement expressions which can be positioned at desired nodes. Wireless test benches take the verification challenge one step further by providing connectivity to physical test instruments from Agilent Technologies. Through this instrument connectivity, a circuit designer can compare the virtual verification with early prototype hardware of their design on the bench, or utilize measured data on the bench for generating more realistic models for simulation.

A wireless test bench (WTB) is a collection of preconfigured, parameterized sources, measurement functions, and post-processing setups based on published specifications of a wireless standard. WTBs offer a seamless verification environment, combining all information that is relevant to verification from sources, circuit DUTs and measurements, and instrument links. WTBs integrate Agilent Ptolemy DSP/baseband simulation with analog/RF circuit envelope simulation in the Cadence flow (Fig. 3). The overall block level representation of a WTB for both transmitter and receiver scenarios includes sources and measurements at RF and DSP levels (Fig. 4). In addition, the Circuit Envelope (CE) simulator in RFDE 2003C contains a new Automatic Verification Modeling (AVM) option to aid simulation of large and complex ICs, allowing computationally intensive BER/PER simulations on large circuits.

Because wireless standards require specific tests, RFDE 2003C includes an extensive set of pre-configured test benches. The preconfigured test benches are for wireless-local-area-network (WLAN), TDSCDMA, and 3GPP formats. In addition, new test benches can be generated and exported from Advanced Design System, making them available to circuit designers for testing and verification.

As an example, simulations of WLAN, PER, and BER measurements were performed on a circuit design of an existing commercial amplifier (MGA 545P8 from Agilent Technologies). The small, low-power amplifier is well suited for 5-GHz WLAN applications, and BER/PER values as a function of adjacent-channel power were of particular interest. Preconfigured test setups were employed once the amplifier's supporting circuit design was ready. WLAN technology (IEEE 802.11a) was selected with a test bench for receiver adjacent-channel rejection. Default values were used for the test source parameters, including 5.2-GHz carrier and 54-Mb/s data rate, source signal bandwidth of 20 MHz, source power of −62 dBm, and variable adjacent-channel power at an adjacent-channel offset of 20 MHz. The simulation time step was set to 1/20 × 8) µs with the AVM option selected. A simulated sweep of adjacent-channel power from −50 to −70 dBm was then performed.

The simulation took less than 10 min per BER/PER point on a Hewlett-Packard computer workstation. Figure 5 shows the BER and PER results as a function of adjacent-channel power. Using these results, one can be more confident of the system-level performance of the circuit design. This process can be repeated as the design size grows with the addition of other modules.

The RFDE 2003C tool also allows Cadence users to generate accurate EM-based models of passive on-chip components and interconnects using Momentum, Agilent's 2.5D EM simulator. With RFDE 2003C, Momentum is integrated into the Cadence Virtuoso (layout) environment, allowing Cadence users to perform EM modeling on select Virtuoso cell(s) as well as physical verification of critical nets (Fig. 6). Full integration into the Virtuoso environment allows designers to extract Momentum cell(s) and back-annotate the EM results to the Cadence schematic.

Momentum computes S-parameters for general passive circuits, including microstrip, stripline, coplanar waveguide, and other topologies. Vias and air-bridges connect topologies between layers, so designers have used Momentum for years to simulate multilayer RF/microwave ICs, printed-circuit boards (PCBs), hybrids, multichip modules, and ICs. Momentum Visualization provides a three-dimensional perspective of simulation results, including viewing and animating the simulated current flow in conductors.

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Traditionally, critical passive elements, such as spiral inductors, have been modeled using simple RLC networks. However, with the resistive loss in the metallization of the spiral coils, the resistivity of the silicon substrate and capacitive coupling effects to the substrate, inductors on silicon behave quite differently than ideal inductive components. With RFDE Momentum, successful design and simulation of wireless RF ICs based on accurate characterization of the electrical behavior of these spiral inductors is possible. Momentum EM simulator models the critical physical parasitics, allowing RF IC designers to design spirals with maximum quality factor (Q) at the desired operating frequency, with the desired inductance value and available substrate "floor space."

The following steps describe a typical process for creating and simulating a design with Momentum. First, a substrate definition file is created and linked to the Technology File of the given process. The designer can then select a portion of the layout and create a "Momentum View." A Momentum simulation is then set up, and the designer can choose between two different modes of operation. Microwave mode suits designs requiring full-wave EM simulations that include microwave radiation effects, while RF mode is for designs that are geometrically complex, electrically small, and do not radiate. Momentum RF mode is also useful for quick simulations on new microwave models where radiation effects are not important, or where computer resource conservation is a priority. After the simulation is complete, the Momentum EM results are saved and can be back-annotated to the schematic (Cadence Composer) for circuit simulation with other passive/active circuit elements.

The Momentum (microwave) and Momentum RF modes use different Method of Moments technologies to produce S-parameter models for layout-based, physical designs. Momentum (microwave) uses fullwave electromagnetic functions based on Maxwell's equations that include substrate and space wave radiation effects. Momentum RF uses quasistatic electromagnetic functions based on low-frequency approximations, which excludes substrate and space-wave radiation effects. Although Momentum RF excludes radiation effects from its resulting models, both modes produce models that include these physical effects: quasistatic inductance, quasistatic capacitance, DC conductor loss, DC substrate loss, dielectric loss, and skin-effect loss. Figure 7 shows a comparison chart of parameters that are calculated by Momentum's microwave and RF/MW modes, as compared with SPICE.

Both modes generate a mesh before simulating the circuit. The resulting rectangular and triangular cells in the mesh are used to compute a set of S-parameters for a circuit. Calculating currents in each cell can require significant computer memory and computation time. However, Momentum uses a mesh-reduction technology to combine rectangular and triangular cells, producing a mesh of polygonal cells (Fig. 8). The reduction eliminates low-quality slivery cells and electromagnetically redundant interactions. The resulting mesh contains far fewer cells, which requires much less computer memory and computation time for a highly accurate set of S-parameters at RF frequencies.

The RF Design Environment provides the time- and frequency-domain tools needed by RF/analog/mixed-signal IC single-chip transceiver designers from within the familiar Cadence design environment. Version 2003C of the RF Design Environment extends these frequency domain simulation technologies to incorporate wireless test benches, and accurate EM-based layout modeling. Agilent Technologies, 30699 Russell Ranch Rd., Suite 170, Westlake Village, CA 91362; (818) 879-6200, FAX: (818) 879-6346, e-mail: [email protected], Internet: www.agilent.com/find/eesof.

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