What you’ll learn:
- How safety-enabled Arm Automotive Enhanced processors address performance in AI-driven use cases.
- Reducing development time and cost with Arm Compute Subsystems.
- The need for virtual platforms.
- How the Arm ecosystem can develop software on virtual prototyping solutions ahead of physical silicon being available.
The heightening demand for more autonomy, advanced user experiences, and integration of software and AI in vehicle electronics makes it more challenging to develop and deliver a product in a timely and cost-effective manner. Addressing those demands, Arm released a variety of Automotive Enhanced (AE) processors along with advanced virtual platforms to significantly accelerate automotive development cycles.
These AE processors bring Armv9 and server-class performance to automotive design. Automotive developers can take advantage of the AI, security, and virtualization capabilities of the latest Arm device architectures, as well as server-class Neoverse technology.
The lineup includes the Arm Neoverse V3AE, which brings Neoverse technology to the automotive sector for AI-accelerated autonomous and advanced driving-assistance systems (ADAS) solutions, and Arm’s first v9-based Cortex-A processors purpose-built for automotive like the Cortex-A720AE for software-defined-vehicle (SDV) applications. There's also the Cortex-A520AE for improved power efficiency with functional safety features scalable across multiple automotive use cases.
The highest-ever-performing real-time processor for functional safety, the Arm Cortex-R82AE, delivers 64-bit computing to real-time processing for the first time, and the Mali-C720AE is a configurable ISP optimized for demanding machine- and human-vision applications. An assortment of configurable system IP is available to aid the Arm silicon ecosystem in delivering scalable, high-performance automotive system-on-chips (SoCs).
Speeding SDV Dev with Virtual Platforms
Virtual platforms enable automotive developers to evaluate IP before it's manifested in silicon, using virtual prototyping to eliminate the need to wait for the physical silicon to be in production. This accelerates the development and deployment of silicon and software in SDVs, hastening their time-to-market, and helps the automotive industry keep pace with the migration to software-defined solutions.
Using virtual platforms along with full-stack software solutions, leveraging the latest generation of Arm AE IP, will save significant time and costs, significantly speeding up development cycles. The virtual platforms were created to address advanced AI-powered vehicle functions like ADAS, in-vehicle infotainment, and the digital cockpit.
The platforms target SoC architecture exploration, helping those developing silicon to explore the SoC architecture in more detail through virtual prototyping, firmware, real-time operating systems, and device drivers for software platform development and integration. This includes OS porting and driver and middleware creation, as well as functionality and application development along with unit testing, supporting software application validation.
Although the new Arm AE IP will be first available on silicon through physical development boards in 2025 and 2026, the immediate availability of virtual platforms allows developers to start virtual prototyping from day one,. Thus, they're able to evaluate design choices before the physical silicon being available. Models of the Arm AE IP can be licensed to EDA partners to build tools that can also be licensed to automotive partners, aiding base software platform development and integration.
In the Cloud and on the Edge
Arm’s EDA and cloud design partners have also released virtual platforms targeting these automotive use cases. For example, Siemens EDA enables accelerated pre-silicon development in the cloud, with hardware-assisted verification using PAVE360 software for SDVs. It's the first accelerated simulation environment supporting the Arm Cortex-A720AE CPU.
Corellium’s modeling technology runs on AWS Graviton in the cloud to deliver functionally representative virtual prototypes of the IP at the high levels of performance needed to support advanced AI workloads. And Cadence is helping create a reference design and software development platform based on its Helium Virtual and Hybrid Studio to accelerate chiplet development for ADAS applications.
Arm’s Neoverse platform is designed to aid in ISA parity, also known as “environmental parity," between the coud and edge, where the same, or near identical, instruction-set architecture (ISA) is used in the cloud and in the vehicle. Built on the Armv9-A architecture, the platform, along with the new Arm AE IP in vehicles, enables ISA parity between cloud and edge.
In addition, it enables automotive applications to be developed in the cloud and then deployed at the edge for faster and more efficient automotive software dev process, accelerating overall quality control and functional-safety certification.
By leveraging cloud-to-ege development approaches, software can be developed in the cloud and integrated with CI/CD workflows for continuous build, test, and validation, with the added benefit of running multiple high-performance workloads in parallel. This streamlines the development process, boosts software productivity, and improves multithreaded workloads across heterogeneous compute domains.
The new virtual platforms will thus significantly reduce time-to-market and solve industry computing and supply-chain challenges, enabling a frictionless automotive development process from cloud to edge.
Arm Compute Subsystems (CSS) for Automotive will deliver pre-integrated and validated configurations of Arm AE IP, optimized for performance and power, in a small footprint. Virtual prototypes let the ecosystem leverage Arm AE IP for software development ahead of silicon availability.
Virtual prototyping on the latest-generation Arm AE IP lets software developers start before the physical silicon is available. This leads to earlier, faster, and more seamless development across the full software stack.