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Discovering ADCs and DACs for Defense Electronics Systems

March 7, 2018
As data converters gain more speed and bandwidth, it presents designers with new opportunities to take fresh looks at applications like radar and communications.

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Defense electronic systems rely on both analog and digital signals and components. And often, in the middle of those systems, highly integrated converters are used to ease the coexistence of analog and digital signals. In spite of the sophistication of their signal-processing chores, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are often taken for granted.

But finding the best ADCs and DACs for an application requires some familiarity with how they work and how performance is described in terms of key parameters. Fortunately, these components are available from a wide range of vendors in many shapes and sizes to serve defense electronics systems, from secure communications systems to surveillance and radar platforms.

An ADC uses sampling to make instantaneous measurements of an analog input signal over its voltage range, converting those measurements into digital words with resolution equal to the converter’s number of bits. The sampling rate takes place at the frequency (or multiple of that frequency) of the clock oscillator used for timing the ADC. A DAC essentially does the opposite, converting digital input code into analog output signals.

The precision and stability of the clock oscillator are important factors in achieving accurate ADC and DAC performance. Both types of converters appear similar, as integrated circuits (ICs) typically supplied in miniature multipin housings (Fig. 1).

1. Analog-to-digital and digital to analog converters (ADCs and DACs) are complex ICs usually housed in multipin packages. (Courtesy of Analog Devices)

ADCs and DACs have a number of performance parameters in common that allow comparisons of different units, including frequency range/bandwidth, sampling rate, and bit resolution. How well each type of component performs the task for which it is designed depends on how well it maintains the accuracy and integrity of the signals it must process throughout the signal/data-conversion processes. In any system, that accuracy will also be impacted by associated components in the signal chain, such as amplifiers and filters on either side of the converter.

For an ADC, its bandwidth is the frequency range of signals that can be measured at its input port. Wider bandwidths allow the capture of higher-frequency signals, although bandwidth is also usually synonymous with cost—ADC costs increase with wider bandwidths and higher frequencies. An ADC designed for use at audio frequencies, such as 20 Hz to 20 kHz, may be low in cost, depending upon other performance parameters, such as bit resolution, but it is also limited in bandwidth. Even in the audio range, a bandwidth of 100 kHz or more may be preferred to include the digitization of higher-order harmonic frequencies.

ADC frequency/bandwidth requirements for defense electronics systems must be carefully considered, so that enough of the input signal can pass from analog form to digital form. These systems range from surveillance and EW systems, where the nature of the signals to be processed may be relatively unknown, to communications systems that may employ advanced forms of frequency- and phase-based modulation schemes.

Samples Simplified

The minimum sampling rate for an ADC is usually determined by the frequency and bandwidth of the signals to be digitized and the number of channels to be digitized. Nyquist theory states that at least two samples are needed to represent the simplest waveforms, so the minimum sampling rate is at least two times the bandwidth of a signal of interest. More samples (a higher sampling rate) bring greater precision by means of a practice known as oversampling (exceeding the Nyquist frequency).

For example, when capturing enough samples on a continuous-wave (CW) signal to provide 90-deg. resolution, four samples per cycle would be needed to capture samples at 90, 180, 270, and 360 deg. per signal cycle. Pulses or more irregular signal waveforms may require more samples per cycle. While it may be true that a defense electronics system’s ADCs will never be accused of capturing too many samples, too few samples per cycle of a signal frequency can result in aliasing errors and an inability to accurately reconstruct that signal into analog form.

The number of ADC samples per signal cycle depends on the allowable average error tolerance, the method of reconstruction of the waveform, and the end use of the sampled data. The actual error of discrete data samples will be impacted by the throughput error of the data acquisition and conversion system, along with any errors contributed by the system’s computer or other digital-signal-processing devices. Increasing the number of samples per cycle for an ADC, or applying different forms of filtering in the system (including at the output of the DAC), can improve the accuracy of the sampled data.

Larger amounts of sampled data deliver increased accuracy when returning the data to analog form through a DAC, although with tradeoffs at the system level. Larger amounts of data require larger memory capacities and potentially slower computer processing speeds, typically resulting in larger size, weight, and power (SWaP) in a system. The faster sampling rates required to generate more data usually translate into higher levels of power consumption.

The number of ADC bits determines the resolution of the data-acquisition system. The number of bits defines the number of digital codes used to represent the original analog waveform. For example, an 8-b ADC uses 256 increments to represent the original analog waveform. A 10-b converter uses 1024 digital codes, while a 12-b converter uses 4096 digital codes.

All ADCs suffer some amount of aperture error, which refers to the amplitude and time errors of the sampled data points for a waveform due to the uncertainty of dynamic data changes during the sampling process. Using high-speed ADCs with fast sampling rates is one way to minimize aperture errors, and fast ADC data-conversion speeds are needed for sampling higher-frequency signals.

The least-significant bit (LSB) of the digital code used in the sampling process also plays a part in determining ADC accuracy, since the digital code produced by an ADC will have an inherent quantization error of ±0.5LSB. That means the analog voltage represented by the digital codes may actually be somewhere between adjacent digital codes. High-performance ADCs can control aperture error to less than ±0.5LSB.

Changing Defense Approaches

Recent trends in ADCs and DACs for commercial and military applications have included wider bandwidths and faster sampling rates. This has allowed system designers to reevaluate their approaches to a particular platform.

Within communications and EW radios, for example, signal sampling has traditionally taken place at the radio’s intermediate-frequency (IF) stage. Moreover, the availability of ADCs with limited bandwidths and sampling rates may have required the use of numerous different frequency-mixer IF stages to downconvert received signals within the input range of an ADC. But as ADCs (and DACs at the output of the receiver) gain in bandwidth and sampling rate, sampling can take place at higher IF, or in some cases, by direct sampling of RF signals.

2. Evaluation boards can simplify the testing of high-speed ADCs like the 14-b model ADC14155, which operates at sampling rates to 155 Msamples/s and typical full-power bandwidth of 1.1 GHz for IF sampling. (Courtesy of Texas Instruments)

Multiple suppliers offer ADCs and DACs with bandwidths in excess of 1 GHz qualified for use across the military operating-temperature range of −55 to +125ºC. As an example, Texas Instruments, which acquired National Semiconductor and its considerable ADC/DAC portfolio, offers system designers its model ADC14155 ADC with 14-b resolution, sampling rates to 155 Msamples/s, and typical full-power bandwidth of 1.1 GHz for IF sampling. It is supplied in a 48-lead, thermally enhanced ceramic package and can be installed on an evaluation board (Fig. 2) for ease of testing. The company’s WaveVision software provides computer control of the data converter.

At even higher frequencies and sampling rates, Texas Instruments’ ADC12DJ3200 family of advanced CMOS ADCs enables direct conversion of RF/microwave input signals to 8 GHz and higher. For example, the 12-b model ADC12DJ3200 ADC can be used as a single- or dual-channel digitizer, with single-channel sampling rates to 6.4 Gsamples/s and dual-channel sampling rates to 3.2 Gsamples/s. With a full-power, 3-dB input bandwidth of 8 GHz and low noise floor for capturing low-level input signals, it is a candidate for receivers in applications from communications and EW to electronic intelligence (ELINT) and radar systems. It enables direct-sampling system designs at S- and C-band frequencies (for more details on the ADC12DJ3200 ADC, click here).

Analog Devices, with its advanced 28-nm silicon CMOS semiconductor technology, has also developed high-speed, high-resolution ADCs and DACs. These enable sampling and signal generation at higher frequencies in commercial wireless communications systems, such as fourth-generation (4G) Long Term Evolution (LTE) cellular communications systems and coming fifth-generation (5G) wireless networks, as well as high-performance military radar and communications systems.  The highly integrated devices include the dual-channel AD9172, which is essentially two RF DACs on a chip (Fig. 3). It is capable of 16-b resolution at sampling rates to 12.6 Gsamples/s for generation of high-resolution analog outputs to 8 GHz and beyond.

3. The AD9172 is essentially two DACs in one package, capable of 16-b resolution and sampling rates to 12.6 Gsamples/s. (Courtesy of Analog Devices)

Additional suppliers of high-speed ADCs and DACs for military applications include CobhamDATELMercury SystemsMicrochip, and Teledyne e2v. Some, such as DATEL and Microchip, provide low-power packaged ICs at competitive prices.

Then there’s Teledyne e2v, which sources its ADQ7DC, a complete ADC data-acquisition module with field-programmable gate array (FPGA) to simplify the chore of adding the digitizing function to a system. The module (Fig. 4) can be specified with one or two channels, 14-b resolution, and sampling rates to 10 Gsamples/s. The company also offers similarly compact modules with DACs for high-speed, low-latency signal generation to 7 GHz and as many as four signal channels per module.

4. The model ADQ7DC is a complete ADC data-acquisition module with one or two channels, 14-b resolution, and sampling rates to 10 Gsamples/s. (Courtesy of Teledyne e2v)

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