*Figure 21* shows the overall predicted noise for the PLL and the contributions from some of the relevant phasenoise sources. *Figure 22* shows the measured phase noise of the test PLL. Note that the close-in phase noise is higher than predicted by the simulation above. This is because the noise floor of the NTS1000A test system has been reached. The instrument's specification sheet lists its noise floor as -40 dBc/Hz offset 10 Hz from the carrier and -74 dBc/Hz offset 100 Hz from the carrier.

*Figure 23* shows the same information plotted on a linear scale similar to what it might look like on a spectrum analyzer. This also allows closer inspection of the noise in the nulls that occur at the sampling frequency and its harmonics. In this analysis, it is also possible to make the oscillator noise higher than the reference/phasedetector/ divider noise to see the effects. In this new example, the far-out phase noise and close-in phase noise will be left unchanged but raise the level of the 20 dB/decade region will be raised by 20 dB, with the resulting parameters (in units in dBc and Hz, respectively) L_{0} = -155; f_{0} = 3 x 10^{6}; L_{2} = -108; f_{x1} = 100 x 103; L3 = -70; and f_{3} = 1x 10^{3}.

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The plot in **Fig. 24** shows the effect of the increase in oscillator noise.

Even though the oscillator noise is above the level of the other noise sources, the effects of sampling in the loop are evident at the harmonics of the sampling frequency.

In the plot of **Fig. 25**, the upper trace shows the measured effect of a relatively noisy oscillator. This is achieved by modulating the VCO with broadband noise to produce the effect of a noisy oscillator. The lower trace shows the normal performance of the PLL.

To continue the analysis, the phasedetector/ divider noise can be made significantly higher than the oscillator noise, at -153 dBc/Hz, to study the effect of the change. **Figure 26** shows the effect of increasing the phase detector noise floor by 10 dB, in a plot of phase noise due to all sources. The same effect would be produced by a noisy reference divider or a noisy feedback divider. (In each case, the noise spectrum is assumed to be flat.)

The upper trace in **Fig. 27** shows the measured phase noise when reference phase noise is raised by 10 dB by modulating the reference VCTCXO with pre-emphasized broadband noise (to produce flat phase noise sidebands on the reference signal). The lower trace shows normal PLL performance.

There are a number of simulation packages provided by PLL chip manufacturers such as ADIsimPLL from Analog Devices and EasyPLL from National Semiconductor. Although they may take discrete time effects into account for the prediction of transient responses, they only use a linear approximation for the loop response and phase noise predictions. For many applications, this simplification may be sufficient for a given design. But with the trend toward faster-settling-time PLLs where the loop bandwidth must be a significant fraction of the sampling frequency, something closer to the true response is required and the analysis presented in this multi-part article can provide a very close estimation of expected performance in sampled PLLs.