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Designing A Low-Noise VCO

Nov. 30, 2004
An inductance-capacitance (LC) voltage-controlled oscillator (VCO) configuration can provide wide tuning range with low power consumption and low phase noise.

Transmitters and receivers for license-free industrial-scientific-medical (ISM) and short-range-device (SRD) bands require fairly high-performance voltage-controlled oscillators (VCOs). For example, ISM and SRD integrated circuits (ICs) must meet the emission limits a such standards as EN 200 220-1, FCC part 15, and ARIB STD-T67. Ring-oscillator1 and relaxation-type VCOs are limited in their ability to support narrowband applications with high output levels at low cost. But inductor-capacitor (LC)-based VCOs can provide good performance at the low costs required by these competitive license-free applications.

Such applications can suffer from several sources of spurious emissions. For example, there are three main sources in a typical phase-locked-loop (PLL)-based transmitter (Fig. 1). The noise of the charge pump is dominant inside the PLL bandwidth. This noise is translated to phase noise via the VCO gain. Outside the loop bandwidth, the noise of the free-running VCO is the dominant noise contributor. VCO phase noise is suppressed inside the loop bandwidth. The third source of spurious emissions is the reference feedthrough signal. It is caused by the nonideal (nonlinear) switching of the charge pump, which leads to a ripple current at the output of the charge pump. As with the VCO phase noise, the reference spurious signals are suppressed by the loop filter.

There are several trade-offs to meet the spurious emission limits. In a ring-oscillator-based VCO, phase noise close to the carrier is usually reduced by the PLL's feedback loop, which has a high bandwidth. But since the loop filter is also designed to suppress reference spurious signals, this leads to problems if high output powers are desired. Furthermore, the noise contribution of the charge pump might be a problem. A better approach involves the use of an inductor-capacitor-based VCO (LC-VCO). Because LC-VCOs have lower phase noise than ring-oscillator VCOs, the bandwidth of the loop filter can be reduced to achieve better suppression of the reference spurious signals, without compromising phase noise close to the carrier. The lower loop bandwidth also reduces the contribution of the charge pump noise.

A similar problem exists for narrowband operation. With an integer-N PLL, narrow channel spacing requires a low reference frequency and narrow loop-filter bandwidth. Therefore, an LC-VCO is necessary when good phase-noise performance close to the carrier is required. Outside the loop bandwidth, the phase noise of the transmitter is only as good as the free-running VCO's phase noise. This is true regardless of the PLL topology.

One way to overcome this problem is the use of an LC-based VCO with an external inductor. By moving the inductor off chip, a smaller IC is possible and higher quality factor (Q) for the inductor. Disadvantages include are increased pin and external component count, increased LC tank parasitics, and the risk of multimode oscillations. These problems cannot be solved by proper IC design alone, but require proper printed-circuit-board (PCB) layout and selection of suitable external components. An LC-VCO with external inductor can save chip area and cost less than an integrated solution, but requires more labor on the part of the user. Thus, a fully integrated LC-VCO is preferred.

A high-quality inductor is critical for the design of a low-power low-phase-noise LC-VCO. Inductors are, however, not readily available in standard integration technologies. One possibility is to use bond-wire inductors. Bond-wire inductors require a length of roughly 1 mm/nH inductance. Because die sizes must be quite small in the competitive market of ISM applications, the realizable inductance values are too small for frequencies as low as 900 MHz.

Therefore, an integrated inductor that uses the metallization system of the integration technology is required. For inductors with a high quality factor, a metal layer with a low resistance is needed. A high substrate resistance is desirable in order to reduce the substrate losses. The used 0.6-µm BiCMOS process offers a power metal option. The third metal layer has a thickness of 2.4 µm and a sheet resistance of 12.5 Ω/square. It is placed 3.5 µm above the substrate. The substrate resistance is 20 Ω-cm.

The VCO is designed with a single inductor to conserve chip area. The inductor is used differentially to achieve a high Q factor. This is also a good match to the differential VCO topology. There exists, however, no support for symmetrical inductors in the Cadence Inductor Modeller.2 Therefore, the inductor was modelled as a non-symmetrical inductor, and the model was then modified according to the several simple approximations. Since the average position of the turns does not change for symmetrical inductors, the inductance value of a symmetrical inductor is approximately the same as for a non-symmetrical inductor with the same geometry. The quality factor will be slightly lower, because of the increased number of via holes. This is modelled through an increased series resistance.

The self-resonant frequency will be significantly smaller, because the oxide capacitance between two adjacent turns now has a much greater contribution to the inductor's parasitic capacitance. Simple estimations suggest that the self resonant frequency of our inductor is only 70 percent of the corresponding non-symmetrical inductor. This is modelled with an additional parallel capacitance. Figure 2 shows the inductor layout and its properties.

The second part of the LC tank is the integrated varactor. In the used process, integrated varactor diodes are readily available. They make use of the junction between a P-diffusion area located in an N-well. The buried collector and sinker are used to achieve a low series resistance for the N-well. The quality factor of the varactor diodes depends on the tuning voltage. At 900 MHz and for a tuning voltage of 2 V, the Q is 70, and reduces to about 35 for a tuning voltage of 0 V.

The cathode of the varactor is located in the N-well, and carries a considerable parasitic capacitance. This parasitic capacitance has a very low Q factor. Therefore, it is important that the anode is connected to the LC-tank, and the cathode is used as control input.

An LC-VCO generally consists of an LC tank and a circuit that generates a negative conductance for compensating the losses in the LC tank. The following equation has to be fulfilled to achieve oscillation start-up conditions:


Gm = the negative conductance of the LC tank and

Rp = the equivalent parallel resistance of the LC tank.

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Usually, a safety factor of at least 2 is used because the conductance value will vary over temperature and with process parameters. A safety factor of 2 requires a minimum current consumption of 0.5 mA for the VCO. An LC oscillator can be modeled simply as a lossy LC tank combined with a noiseless energy restorer that keeps a constant oscillation amplitude. The phase noise for this model is

which is the theoretical limit for an LC oscillator (flicker noise being neglected). In reality, a noiseless energy restorer is not possible. There will be further noise contributions that usually dominate the oscillator phase noise. The goal for the LC-VCO design is to reduce these contributions and approach the noise limit as closely as possible.3 The power dissipated by a lossy parallel LC-tank is

The LC-VCO circuit (Fig. 3) is strongly nonlinear for oscillation amplitudes higher than several tens of mV, and restores the energy approximately with a constant current of Isupply/2 during each half cycle. The power restored to the LC tank is

The oscillation amplitude will build up from noise until the dissipated power is equal to the restored power. Under steady-state conditions, the peak voltage is

For a current consumption of 1.35 mA, these equations yield an oscillation amplitude of Vpeak = 525 mV. Therefore, the theoretical phase-noise limit is -88.3 dBc/Hz at an offset frequency of 10 kHz.

The LC-VCO core circuit is based on a cross-coupled bipolar transistor pair, which creates a negative conductance. For the same transconductance value, bipolar transistors exhibit lower current consumption than MOS transistors. Biasing is performed via two current sources from the positive power supply instead of one current source from the negative power supply. By doing so, only one inductor is needed.

Care must be taken so the base-collector junction of the bipolar transistors does not become forward biased, or performance can be degraded. In this case, the real part of the input impedance will be degraded and decrease the LC-tank Q (thus increasing phase noise). Also, the transit time of the transistor will be increased. As a result, the two current sources will see unequal time-variant load impedances. This causes the VCO to act as a mixer, and to upconvert bias noise to the oscillation frequency. Therefore, the collector potential must always remain above the base voltage. One way to achieve this is by connecting the bases to the collectors via emitter followers. Unfortunately, this approach adds noise. A better method is by AC-coupling the device bases; the bias voltage is generated from the average of the two collector voltages by using an emitter follower.

To maintain high Q, the varactor diodes must be reverse biased. By AC-coupling the varactors and setting the bias voltage from cathode to ground, the full voltage range from 0 V to the positive supply voltage can be used for the tuning voltage. By AC-coupling the varactors, the bias upconversion noise is reduced even further. To control low-frequency bias noise, the biasing resistor short-circuits the nonlinear varactor diode.

To achieve a resonant frequency of 868 MHz with a 12-nH inductor, a capacitance of 2.8 pF is required. The VCO circuit exhibits 0.6-pF parasitic capacitance, while the coupling capacitors are MIM components with 20 pF value, which requires a capacitance of 5.6 pF for each varactor. The values of the biasing resistors are chosen for optimal phase noise. This choice is a trade-off between the A and the noise generated by the resistors. Since calculating an optimum value would be time-consuming, optimization was performed with periodic steady state (PSS) and periodic noise (PNoise) analysis tools from Cadence Design Systems (San Jose, CA). The coupling capacitors and bias resistors influence both the overall Q and the negative conductance. Following optimization, it is necessary to verify that the start-up condition is still satisfied with a sufficiently high safety margin.

After optimization, the simulation shows that the main noise contributors of the VCO circuit are the losses of the LC tank and the active elements of the VCO core circuit. Bias noise has no significant influence. The VCO has a center frequency of 860 MHz and a tuning range of 150 MHz (17 percent). The simulated phase noise is -82 dBc/Hz (at an offset frequency of 10 kHz), which is about 6 dB above the theoretical limit. This is because the theory does not account for the additional noise sources in the active and passive VCO circuit elements. The VCO operates in a wide supply voltage range from 2.2 to 5.5 V, and consumes only 1.35 mA. Figures 4 and 5 show simulations of the tuning characteristics and phase noise, respectively.

For evaluation purposes, this VCO was integrated into an existing commercial FSK/ASK 900-MHz transmitter IC.4 The transmitter IC (Fig. 6) is based on a PLL with a fixed divider ratio of 32. FSK modulation is achieved via reference oscillator modulation by pulling the reference crystal oscillator. This modulation method can handle code formats with and without DC content (e.g., NRZ and Manchester code). ASK modulation is achieved by turning on and off the power amplifier. Only few external components are needed to build a complete ASK or FSK transmitter.

With the lower phase noise achieved by the new VCO, it is possible to reduce the bandwidth of the PLL from approximately 700 to 200 kHz, reducing the phase noise of the complete PLL from -87 to -92 dBc/Hz offset 100 kHz from the carrier and from -90 to -110 dBc/Hz offset 1 MHz from the carrier (Fig. 7). This allows for narrowband applications requiring low adjacent channel power leakage and addresses applications with output powers in excess of 10 mW.


  1. A. Laute, "Two 868 MHz Transmitter ConceptsA Comparison Between SAWs and PLLs," Proceedings Radio Solutions 1999, Birmingham, England.
  2. Xiaojun Zhu, "Modeling and Simulation of On-Chip Spiral Inductors and Transformers,"
  3. T.H. Lee, A. Hajimiri, "Oscillator Phase Noise: A Tutorial," IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, pp. 326-336, March 2000.
  4. Melexis RF products,

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