Speedy Switches Minimize Gate Lags

March 18, 2010
These novel GaAS pHEMT microwave switches minimize gate lag times from almost 30 ?s to less than 20 ns by applying a patent-pending semiconductor process.

Andrew Freeston, Timothy Boles, Costas Varmazis

Switching speed is a complex parameter that includes a number of events, each with its own duration. By means of a patent-pending pseudomorphic-high-electronmobility- transistor (pHEMT) technology, M/A-COM Technology Solutions has found a way to dramatically shorten the duration of one of these eventsa switch's settling timeto the benefit of systems requiring tight control of time-domain parameters, such as packet-based communications networks and radar systems. The technology is available in a line of switches operating from 10 MHz to 20 GHz with settling times as fast as 20 ns.

Switching speed and settling time or "gate lag" both describe high-speed switch performance, but the parameters differ and are often misunderstood. Switching speed is a change in state from 10 to 90 percent of an RF envelope when a switch is turned from "off" to "on" by a control signal, with a certain rise time to the change of state (Fig. 1). The time from the point at which the control signal is at its 50-percent point until the RF envelope is at its 90-percent point is traditionally denoted as ton The time for the envelope to change from 10 to 90 percent of its value is the rise time and denoted as trise. When a switch is turned from "on" to "off" by a control signal, toff is the time from a 50-percent change in the control logic to the full transition from 90 to 10 percent of the RF envelope, while tfall is the time for the transition only, from 90 to 10 percent of the RF envelope. Gate lag defines the settling-time characteristics of a switch past its 90- or 10-percent points.

Unfortunately, the last 10 percent of a switch's transition time can make traditional switchingspeed specifications misleading, since the last10 percent has a different slope than the first 90 percent. Historically, the response is fairly logarithmic, approaching the fully settled value. Typically, for a switch with a 90-percent point of 10 ns, the 100-percent point may require hundreds of milliseconds. This long settling time, known as gate lag, poses problems for many systems.

Device gate lag can be measured as the change in RF power through a device from 90 percent of the settled value to some point later, such as 97.5 or 100 percent, depending on available equipment and methods. It can also be observed as a change in resistance between two fixed time points after the control signal changes, since a switching device exhibits low resistance in the "on" state and high resistance in the "off" state. For example, the gate lag of a device may be described as a 0.5-Ohm variation from 10 s to 10 ms after a change in the control signal. Although gate lag cannot be eliminated, M/A-COM Technology Solutions has developed its own solution for minimizing delays due to gate lag.

Whether seen as delays or variations in switch impedance, high-speed switching is essential in many test applications as well as in other systems. Some complex packet-based modulation schemes rely on fast transmit/receive or diversity switching to optimize data throughput and reduce the signal-to-noise ratio. If the switch is still settling when the first packet is transmitted through it, the envelope shape could be rounded, potentially compromising the data. For high-data-rate communications applications, rapid settling performance quickly can allow for reductions in waiting time prior to transmitting. More available time for data transmission results in improved throughput.

Fast-settling-time switches can also bring thermal benefits. When RF power is applied to a device that is not fully settled, there will be significantly more power dissipation until reaching steady state. Faster settling means less power dissipation due to unsettled series resistance, and cooler operating junction temperatures at high power.

Switching delays are primarily related to a time-dependent charge/discharge decay effect of changing a static charge that is stored in the active device and its associated circuitry. Several things cause the lag to be present, and can be described in terms of resistance and capacitance. A FET gate is small in size and somewhat lossy. Because a large-value gate resistor is typically used in most switch designs for DC-to-RF isolation, it contributes to a resistive-capacitive (RC) time constant. For any transition in state (as a first-order approximation), the device channel must be depleted or restored, and the field around the gate must be created or removed.

At the device level, switching speed and any associated gate lag can be understood by reference to a simplified cross section of a GaAs MESFET/pHEMT (Fig. 2). The RF switching time is dominated by the charge in the channel region, in both the gated and ungated recess regions adjacent to the gate. The device turn-on time is the time required to move charge from the source through the channel region to the drain after application of a control signal. The turnon time is a function of the delay associated with filling the channel region with charge. This includes channel charge associated with the gate capacitance and surface trap charge in the ungated recess region. The turn-off time is the reverse, with full turnoff not complete until all charge is removed from the channel and recess regions.

This device cross-sectional diagram also makes it possible to visualize the relatively fast trise, RF envelope going from a 10 to 90 percent level, and tfall times, RF envelope going from a 90- to 10-percent level, and the comparatively very long gate lag times for the transition from a 90- to a 100-percent RF envelope. The majority of the charge is associated with the channel charge in the depletion region directly under the gate. This charge can be moved into and out of the gate region relatively quickly by applying the proper polarity bias on the gate terminal. On the other hand, the charge in the ungated recess region is tied up in surface states and interface traps and is relatively insensitive to applied bias and can only be charged or discharged through the resistive-capacitive (RC) circuit formed by the Schottky diode gate. This filling or unfilling of these surface charges is a slow process and leads directly to the long gate lag switching times.

To address these issues with the long RF switching times associated with the long times associated gate lag dominated change of state, a number of changes were made to the existing pHEMT process used to fabricate microwave switches. These changes are shown in the cross section of the improved pHEMT device (Fig. 3). The number of surface states and interface traps were reduced at the ungated GaAs surface via a combination of cleaning techniques and the deposition of a passivating dielectric. Also, the formation of the Schottky diode gate was modified to both reduce gate resistance with no additional gate capacitance and to minimize the RC charging time associated with device turn on and turn off. Lastly, a proprietary III-V layer was added to the pHEMT structure to further reduce the channel resistance and enable enhanced movement of charge through the device especially from the ungated recess region. This process optimization results in a dramatic improvement in switching speed over standard pHEMT devices. The patent-pending process yields settling-time characteristics that are dramatically improved compared to existing switch products (Fig. 4), without significantly impacting other device parameters.

Figures 4 and 5 show measurements of Ron versus time for switching FETs manufactured with a standard pHEMT process and with the process optimized for low lag switching. The on-resistance performance and deviceto- device variations are dramatically improved with the new process. Waferto- wafer switching characteristics are also much more consistent with the new process. It is important to consider that in the isolated, or "off" condition, the device has thousands of Ohms of resistance. A device could hit the 90-percent point rapidly, yet still have a long way to go to be settled: the absolute range of change is very large. On high isolation switches that are manufactured with a standard pHEMT process, the standard switching speed specifications can be misleading, since the transition is proportional to the absolute signal level variation. The sharper turn-on characteristics of the low gate lag process provide dependable rapid transitions.

To gauge the speed benefits from the new process, a typical pHEMT switch was compared to switches fabricated with the new process. A time of 274 s was observed for the typical pHEMT switch to go from 90 to 98 percent of the RF envelope. With the optimized pHEMT process, which includes the proprietary III-V low gate lag layer, the total gate lag delay for the same 90- to 98-percent was only 18 ns (Fig. 5).

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The table provides a performance summary for a group of switches with fast settling times, from 10 MHz through 20 GHz (Fig. 6). The fastest of these devices is model MASW-009590, a single- pole, double-throw (SPDT) switch die with 97.5-percent settled point of about 20 ns. It is usable from 10 MHz to 8 GHz with 0.6-dB insertion loss and 23-dB isolation, It can handle +30 dBm power at 1-dB compression when running from a +3-VDC supply. This switch family includes parts that are high power, others that are very broadband, and one with very high isolation.

Gate lag is an important parameter in test systems, packet-based data transmissions, radar systems, and many other applications that are time-variation critical. This new switch family offers fast settling-time performance as a result of semiconductor fabrication process optimization that can dramatically reduce the total switching time with excellent electrical performance. M/A-COM Technology Solutions, 100 Chelmsford St., Lowell, MA 01851; (978) 656-2500, Internet: www.macomtech.com.


The authors wish to acknowledge the assistance and support of the M/A-COM Technology Solutions wafer fabrication personnel and engineering staff.


1. A. F. Basile, A. Mazzanti, E. Manzini, G. Verzellesi, C. Canali, R. Pierobon, and C. Lanzieri, "Experimental and numerical analysis of gate- and drain-lag phenomena in AlGaAs/ InGaAs PHEMTs," 10th IEEE International Symposium on Electron Devices and Optoelectronic Applications, EDMO 2002, pp. 63-68.

2. S. Dhar, V. R. Balakrishman, V. Kumar, and S. Ghosh,"Determination of energetic distribution of interface states between gate metal and semiconductor in sub-micron devices from current-voltage characteristics," IEEE Transactions on Electron Devices, Vol. 47, Issue 2, pp. 282-287, February 2000.

3. A. Freeston, "Understanding Gate Lag and How it Differs From Switching Speed," Microwave Product Digest, September 2008.

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