Linearize Power Amps With RF Predistortion

Aug. 12, 2011
The use of RF predistortion can improve the linearity of power amplifiers at power levels as low as 500 mW over a wide range of operating conditions for maintaining low system power consumption and cost.

Linearity is a key to multimode, multicarrier wireless networks, including wideband third-generation (3G) and fourth-generation (4G) cellular systems, including small cellular base stations with reduced coverage areas and low transmit-power architectures. The spotlight is on RF/microwave power amplifiers (PAs) to deliver the required performance at low cost and low system power consumption. Unfortunately, PAs are not typically linear in behavior, and cost-effective means to linearize PAs operating at average output power of 0.5 to 60 W have simply not been available. But a solution has surfaced, in the form of a family of RF power amplifier linearizer (RFPAL) system-on-chip (SoC) solutions from Scintera which apply predistortion to achieve improved linearity in Pas operating at power levels below 60 W. Especially below 10 W, where most PAs are based on Class A or AB biasing arrangements, these RFPAL circuits offer a compelling alternative to the use of back-off. To better understand the use of these RFPAL solutions and their use of RF predistortion (RFPD) technology, they will be compared to the digital predistortion (DPD) and back-off methods traditionally used to improve PA linearity.

No PA is perfect. When fed a multitone input signal, the PA will boost the desired signal but will also generate undesired intermodulation (IM) terms (Fig. 1a). This nonlinear behavior increases as the PA approaches saturation. To achieve acceptable linearity without predistortion, a PA is usually backed off from its saturation point

SAT(3 dB) in Fig. 2a>. Unfortunately, the amplifier's DC efficiency decreases as its operating point is backed off (Fig. 1b). Efficiency of 8% or less is not unusual for a Class AB PA that has been backed off to accommodate the signal's high peak to average ratio (PAR) and the further back-off to meet system linearity requirements.

For many cellular communications applications, PAR is based on a complementary cumulative distribution function (CCDF) probability of 10-4. Considering that backing off an amplifier is the most popular linearization approach for PAs transmitting 20 W or less average power, active linearization is quite appealing as a practical alternative. Active linearization technologies, including RFPD and DPD, allow the transmitter to operate close or even slightly above its PSAT - PAR operating point (Fig. 2b). Of course, no predistortion approach can correct signals when their peaks extend beyond a PA's saturation point, since there is no way to recover the information lost due to clipping. With active linearization, a Class AB amplifier can typically be driven 3 to 6 dB harder to improve efficiency by 2x to 4x. Compared to backing off an amplifier, active linearization enables the final stage PA, power supply, cooling elements, and operating costs to be reduced by one-half or more.

In systems requiring wide signal bandwidths, such as Long Term Evolution (LTE) systems, or in wideband multicarrier/ multiprotocol systems, backing off a PA may not be an option since the PA may not achieve the desired linearity at any power level. In these systems, active linearization is necessary to meet the regulatory radiated emission or communications standard's requirements. When taking into account system cost, power consumption, size, etc., RF predistortion can realize such requirements in systems where the PA operates at average output power levels as low as 500 mW.

The SC1889 and SC1869 SoC RFPALs from Scintera represent a practical solution for achieving linear performance in small cell designs, where reduced system cost, footprint, and complexity are important factors for the deployment of heterogeneous networks. Within such networks, this RF predistortion technology provides a cost-effective alternative to DPD or backoff approaches for PAs operating at maximum average output power of about 0.5 to 60 W. The SC1889 supports instantaneous bandwidths to 60 MHz and can be used with either Class A/AB or Doherty amplifiers operating between 5 and 60 W average output power. The SC1869 supports instantaneous bandwidths to 20 MHz and is optimized for use with Class A/AB amplifiers transmitting between 0.5 and 10 W average output power.

The RF predistortion technology embodied in the SC1889 and SC1869 devices shares similarities with DPD in that both compensate for amplitude-modulation-to-amplitude-modulation (AM-AM) and amplitude-modulation-to-phase-modulation (AM-PM) distortion, intermodulation, and PA memory effects; also, both employ feedback information to compensate for impairments due to temperature variations and PA aging. Although both RF predistortion and DPD are based on Volterra series approximation and share other underlying theoretical similarities, the similarities end with their circuit design and system implementations.

The SC1889 and SC1869 RFPALs are adaptive systems that work with RF input and output signals (RFIN and RFOUT) so that they enable standalone operation in remote radio heads, PA modules, and any application without direct access to a digital processor. As an example, Fig. 4a shows a high-level system block diagram using an RFPAL. In the block diagram, directional couplers are used to drive the linearizer's RF inputs (RFIN and RFFB). The correction signal (RFOUT) is then combined with the PA input signal by means of a direction coupler. The linearizer uses the PA output signal to adaptively determine the nonlinear characteristics of the PA at a given average and peak power level, center frequency, and signal bandwidth. This feedback signal (RFFB) from the PA output is analyzed in the frequency domain to generate a spectrally resolved linearity metric for adaptive correction of the cost function.

The RFPAL processor generates the correction signal based on a Volterra series approximation that is continually optimized through a set of programmable coefficients generated by the digital controller. The digital controller runs an adaptation algorithm and applies the coefficients to the correction processor to minimize the cost function. As shown in Fig. 4b, the entire linearizer system (including all components within dashed lines of Fig. 5a) can be realized in a compact printed-circuit-board (PCB) footprint measuring less than 6.5 cm2 and with a low bill of materials (BOM).

With a baseline established for an RFPD's basic operation, the larger system can be described and compared to the use of DPD amplifier linearization approaches. Figure 5 illustrates how DPD expands the bandwidth (adds the predistortion correction signal to the desired signal) at the earliest point in the signal chain, at digital baseband. That bandwidth expansion is then propagated through the entire transmitter chain and back again through the feedback path to the digital baseband. The bandwidth expansion burdens the entire system with increased clock speeds and expanded component bandwidth requirements leading to higher system power consumption. Added complexities include (but are not limited to) challenging clock generator requirements, including jitter performance, adding the need for a multipole high-frequency reconstruction filter, and the need for a wideband linear frequency upconversion mixer.

With DPD systems, the frequency response of the filter after the upconverter must be wide enough to accommodate the desired signal plus the bandwidth expansion required for the PA predistortion. Unfortunately, any noise generated by the digital-to-analog converters (DACs), frequency upconverters, etc., within the filter's pass band will also be amplified by the PA. In the majority of applications, the only way to filter the noise falling within the receive band is at the output of the PA. This requires the use of filters whose size, cost, and insertion loss varies based on the design requirements. There is also a potential increase in the cost of the filter to meet the more stringent rejection requirements. Any added insertion loss due to this filter degrades efficiency and requires the PA to be driven harder to achieve the same output power at the antenna as originally desired. As a result, the filter partially negates the benefits that were achieved through the use of DPD. Alternatively, lower noise DACs and upconverters may be used to minimize the need for a post-PA filter, but at higher cost and current consumption than their highernoise counterparts.

Note, that power consumption is estimated based on an integrated DPD/DSP application-specific integrated circuit (ASIC) and external analog-to-digital converters (ADCs), DACs, downconverter, clock generator, and power detectors. The power consumption estimates do not include the digital upconverter (DUC), crest-factor-reduction (CFR) circuitry, and PA since they are present in both DPD and RFPD implementations.

By leveraging a standalone RFIN/ RFOUT architecture and adaptive RF predistortion technology, Scintera's integrated approach allows the correction signal to be injected only at the point it is needed, at the PA's input port. The benefits of this implementation can be seen in Fig. 6. The requirements on the clock generator, reconstruction filter, and upconversion mixer are all relaxed while all the components in the transmitter chain from the digital baseband up to the PAs can operate at 1x signal bandwidth. However, the linearizer can operate with a signal bandwidth greater than 5x with no system design or power consumption penalty since far out residual intermodulation products can be easily filtered. The total predistortion bandwidth of the SC1889/69 is about 250 MHz, enabling compensation to eleventh-order IMs for an instantaneous bandwidth (desired signal) of 20 MHz, or to fifth-order IMs for an instantaneous bandwidth of 50 MHz. Additionally, the RFPD-based system needs only a narrowband filter before the PA, relaxing the DAC and upconverter noise requirements, and avoiding costly filtering at the PA output. Although not required for a RFPD implementation, the SC1889/69 RFPALs also integrate the entire RFFB feedback path, thus greatly simplifying the overall system design and limiting the active components affected by the bandwidth expansion to just the PA and the linearizer. These benefits lead to very low power consumption and a greatly simplified, lower-cost transmitter and baseband architecture.

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In the example given, the RFPD implementation consumes 4 W less than the DPD implementation. Although the power difference may not be a critical issue in macrocell designs, the reduced power consumption, lowered system cost, and smaller footprint of RFPD-enabled designs become important factors in microcell, picocell, and enterprise femtocell designs. The SC1889/69 SoCs also include optional features which provide measurement functionality for forward and reverse power and for monitoring temperature and spectral-mask conditions, to further simplify system implementation.

Scintera's approach to RF power amplifier linearization is to repartition portions of the predistortion algorithm from the digital domain to the analog/RF domain. Nearly the entire correction processor block of Fig. 7 is implemented using RF/analog circuits including those shown in Fig. 8a, resulting in very low power consumption, wide bandwidth performance, and compact circuits compared to the equivalent digital implementations.

Starting with the correction processor block, the RFIN signal passes through a quadrature phase shifter (QPS) to create in-phase (I) and quadrature (Q) signal components , which are used in multiple locations. The envelope power of RFIN (I) and RFIN(Q) is also used in the Volterra series generator block to create the even-order IM terms by applying a nonlinear transformation. To compensate for PA memory effects, four different sets of coefficients are created based on delay terms τ1 to τ4, ranging from 0 to 300 ns (Fig. 8a). All coefficients are individually controlled and generated by the digital controller running a proprietary adaptation algorithm. For each of the memory terms, the even-order correction functions are summed and then multiplied with their corresponding RFIN(I) and RFIN(Q) signals generated by the QPS. This final multiply converts the even-order terms into odd-orders terms. The I and Q correction signals are then summed to create the RFOUT correction signal. The correction processor uses a full 360-deg. modulator enabling it to correct IM terms of any phase and magnitude. The digital controller adapts the coefficients based on the information derived from the RFFB feedback signal and applies them to the correction processor until an optimal set of coefficients is found that minimizes the cost function (error metric).

The monitor block is implemented largely in the digital domain, since functions like Fast Fourier Transforms (FFTs) and error metric generation are better suited to implementation using digital signal processing (DSP). As seen in Fig. 7, the monitor inputs include the downconverters and ADCs required to provide the spectrally resolved data used by the DSP. Integration of the RFFB ADC is a significant difference compared to a DPD which relies on external downconverters and ADCs. The unique partitioning approach employed in the SC1889/69 SoCs results in a monolithic and highly integrated solution that maintains the flexibility of digital approaches, while offering the simplicity and low power consumption of analog approaches.

Many factors determine the overall performance of any linearization solution. The greatest benefits for the RFPAL approach can be realized as an alternative to backing off a PA. Consumption of just 0.4 W power for the RFPAL brings back as much as 4x improvement in efficiency compared to backing off a PA, enabling proportional decreases in overall system power consumption. Additionally, linearization enables operation of the PA closer to its PSAT operation point, allowing the use of smaller transistors to achieve a desired output-power goal. Reducing power consumption reduces the annual operating cost (electricity) of a system which, for antenna power levels greater than 5 W, can offset the initial cost of the RFPAL solution in a relatively short time.

The table shows that the system power consumption and system efficiency advantages over the use of backed-off amplifiers are clear: a 3x improvement in efficiency, a system power reduction of over 67 W, and a yearly operating cost saving of almost $30. Although not every system will operate at maximum output power all the time, the power supply capacity and system cooling requirements must be designed for worst-case conditions. An often overlooked benefit of predistortion techniques, compared to operating a PA in backed-off mode, is the dramatic reduction in size/volume and costs associated with the power supplies and cooling elements (heatsinks, fans, etc.).

An important difference is apparent when comparing the RFPAL approach against DPD techniques. Even when DPD provides better final-stage PA efficiency than the RFPAL approach (2% better in the table, but the difference in most cases is much smaller), the overall system efficiency is worse with DPD than RFPAL due to the DPD method's higher power consumption. As antenna output power levels drop below 10 W and approach 0.5 W, the improvement in system efficiency grows progressively larger for RFPAL due to the DPD power consumption becoming a larger portion of the overall system power consumption. This difference can be seen using Scintera's efficiency calculator available online at With similar correction performance to DPD, but improved power consumption and efficiency, reduced complexity, lower system cost and a small footprint, RFPAL is an ideal choice for small cell designs, which are part of heterogeneous deployments.

In comparing these various PA linearization approaches, it is important to realize that there are analog-based applications that can not make use of DPD, such as analog remote radio heads, PA modules, repeaters, and microwave backhaul systems. Because the RFPAL approach is an adaptive RFIN/RFOUT and standalone linearization solution that requires no external digital control, it is well suited even for all-analog systems. The digital port shown in Fig. 4a is optional and used in applications where reporting functions are desired and not needed for the analog applications mentioned above. The SC1889/69 is simple to integrate and requires no expertise in predistortion algorithms, making it a realistic alternative to operating a PA in backed-off mode.

The SC1889 and SC1869 SoCs are suited to cellular applications from 470 to 2800 MHz, with PAR to 10 dB, static average power waveforms like CDMA and WCDMA, dynamic average power signals like WiMAX, HSDPA, and LTE, and a wide range of PAs, including Class A/B or Doherty amplifiers, based on different process technologies, such as silicon LDMOS, GaN, and GaAs device technologies. The devices embody predistortion technology and feedback techniques that can compensate for the effects of distortion resulting from AM-AM, AM-PM, intermodulation, and even PA memory effects. The SC1889 and SC1869 RFPALs are adaptive systems that process input signals and provide output signals for a communications system, enabling standlone operation in remote radio installations. Their application offers a practical alternative to the use of back-off techniques for achieving improved amplifier linearity. Both devices can be operated over a wide case temperature range of -40 to +100C. The company has developed products for microwave radio and broadcast infrastructure markets, with RFPAL circuits integrated into DVB-T, ATSC, and CMMB transmitters operating at greater than 600 W average output power. The RFPAL technology is also suitable for such communications platforms used in military and public safety systems.

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