Image

60-GHz IPIC-QVCO Reduces Phase Noise And Error

April 3, 2014
Researchers from Singapore have designed and tested a 65 nm CMOS quadrature PLL operating at 60 GHz using an IPIC-QVCO typology for reduced phase noise and phase error.  
Download this article in .PDF format
This file type includes high resolution graphics and schematics when applicable.

Designing a low-power CMOS phase-locked loop (PLL) operating at 60 GHz for a direct-conversion transceiver is quite tricky. For example, it is difficult to account for low phase noise/phase error and the wide-range operation necessary for high-data-rate wireless communications. To meet those design challenges, a research group from Singapore developed an integer-N, third-order, charge-pump PLL with a 135-MHz reference and an in-phase, injection-coupled (IPIC) quadrature voltage-controlled oscillator (QVCO). A paper describing the design of the IPIC-QVCO has been provided by Xiang Yi, Chirn Chye Boon, Hang Liu, Jia Fu Lin, and Wei Meng Lim.

An in-phase, injection-coupled, quadrature voltage-controlled-oscillator circuit is proposed to enhance phase noise and error for 60-GHz frequency synthesizers.

A benefit of this design is that quadrature accuracy is not affected by the mismatches of the Q of the tank circuit and the current reference. But the mismatch of the coupling network does affect the quadrature accuracy as a function of phase error. Because the coupling network is composed of a symmetric design, the mismatches produced are minimal. In terms of phase error, this amounts to less than a 1 deg. error with a maximum 5% mismatch in the coupling network.

The circuit was simulated with 65-nm transistors, as they meet the frequency requirements of 60-GHz transmission. In a comparison with other simulated typologies of QVCOs, the IPIC-QVCO supposedly outperforms P-QVCOs, super-harmonic-coupled QVCOs, and magnetically coupled QVCOs when it comes to phase-noise and phase-error metrics. The experimental circuit in 65-nm CMOS covers 57.9 to 68.3 GHz while boasting phase noise from -89.8 to -91.0 dBc/Hz at 1-MHz offset from the carrier throughout the frequency of operation. See “A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology,” IEEE Journal Of Solid-State Circuits, Feb. 2014, p. 347.

Download this article in .PDF format
This file type includes high resolution graphics and schematics when applicable.
About the Author

Jean-Jacques DeLisle

Jean-Jacques graduated from the Rochester Institute of Technology, where he completed his Master of Science in Electrical Engineering. In his studies, Jean-Jacques focused on Control Systems Design, Mixed-Signal IC Design, and RF Design. His research focus was in smart-sensor platform design for RF connector applications for the telecommunications industry. During his research, Jean-Jacques developed a passion for the field of RF/microwaves and expanded his knowledge by doing R&D for the telecommunications industry.

Sponsored Recommendations

MMIC Medium-Power Amplifier Covers 6 to 12 GHz

Nov. 11, 2024
Mini-Circuits is a global leader in the design and manufacturing of RF, IF, and microwave components from DC to 86GHz.

RF Amplifier and Filter Testing with Mini-Circuits Power Sensors

Nov. 11, 2024
RF power sensors are essential for accurately measuring RF components like filters and amplifiers, focusing on parameters such as insertion loss and gain. Employing instruments...

High-Frequency Modules to 110 GHz

Nov. 11, 2024
Mini-Circuits’ wide selection of high-frequency modules are designed, assembled and tested in-house by the best talent in the industry at our Deer Park Technology Center. The ...

Defense Technology: From Sea to Space

Oct. 31, 2024
Learn about these advancements in defense technology, including smart sensors, hypersonic weapons, and high-power microwave systems.