Advanced Phase-Lock Techniques

May 13, 2008
Phase-locked loops (PLLs) are an integral part of many communications systems. Essential for their capability of synthesizing stable output signals from tunable oscillators, such as voltagecontrolled oscillators (VCOs), the PLL has grown in ...

Phase-locked loops (PLLs) are an integral part of many communications systems. Essential for their capability of synthesizing stable output signals from tunable oscillators, such as voltagecontrolled oscillators (VCOs), the PLL has grown in importance with the growing use of digital modulation formats and design requirements to compress more information onto transmitted RF/microwave signals. For those seeking a comprehensive roadmap to the world of PLLs, there may be no better source than the recently released Advanced Phase-Lock Techniques by James Crawford.

The 510-page text opens with a high-level perspective of phase-locked systems. This first chapter includes closed-form solutions for discrete PLL designs, and covers some basic communications theory. It outlines the use of estimation theory to design nearly optimal PLL systems.

The following chapter presents design equations, including a summary of the classic continuous-time second-order PLL design equations, such as the open-loop gain function, the closed-loop gain function, the open-loop 3-dB frequency, the closed-loop unity-gain frequency, the closed-loop maximum gain, the phase margin, the equivalent noise bandwidth, and expressions for the transient response. Equations and plots are also presented for communications theory fundamentals, including plots showing the effect of a noisy oscillator on binary-phase-shift-keying (BPSK), 16-state quadrature-amplitude-modulation (16-QAM), and 16-state phase-shift-keying (16-PSK) system bit-errorrate (BER) and symbol-error-rate (SER) performance.

Chapter 3 provides fundamental limits on the design of time and frequency control systems. This section helps designers understand practical margins between theoretical performance limits and the performance requirements of a particular PLL design. It covers phase margins, the effects of RF filtering on frequency stability, application of Eigenfilters, the Fano broadband matching theorem (which states that a fundamental limit exists between bandwidth and a network's reflection coefficient behavior with respect to frequency), the Leeson-Scherer phase-noise model, and the Nyquist sampling theorem.

Chapter 4 highights noise in PLL systems: how it is generated, how to characterize it, and how to model it. Ironically, the remainder of the book focuses on how to minimize noise in PLL designs, but this chapter details the sources of noise in PLL systems. It covers such noise sources as semiconductors (including their noise components, such as thermal noise, shot noise, and flicker noise), quantization noise in data converters, and time-sampled noise. This chapter also reviews first principles for phase noise, how to characterize phase noise, and how to model phase noise in PLL systems. The chapter also provides a useful appendix with additional information on how to create arbitrary noise spectra in a digital-signal-processing (DSP) environment and how noise is generated in direct-digitalsynthesizer (DDS) source.

Chapter 5 presents an overview of PLL system-level performance. It details, for example, how local oscillator LO) phase noise can be detrimental to receiver performance. It describes the effects of close-in phase noise on receiver performance, as well as the system-level effects of phase noise at large frequency offsets. It also reviews the effects of close-in and larger-offset phase noise on transmitter system performance, and how phase noise can adversely affect the BER performance of a digital communications system.

For designers developing sources for next-generation wireless-local-area-network (WLAN) systems, this chapter includes a useful section on the phase-noise effects on orthogonal-frequency-division-multiplex (OFDM) systems and how to calculate channel estimation errors due to phase noise. It includes studies on the effects of clock phase noise on digital-to-analog-converter (DAC) and analogto- digital-converter (ADC) performance levels. Chapter 5 includes a useful appendix, which details the use of errorvector- magnitude (EVM) measurements in understanding amplitude and phase errors on modulator performance.

Chapter 6 presents fundamental concepts for continuous- time PLL systems, with useful details on a variety of simple and more complex loop filters. It includes coverage of pseudo-continuous phase-detector models, and explains how to perform a stability analysis on a continuous-time PLL system. Chapter 7 offers fundamental concepts for sampled-data control systems, and includes a stability assessment for sampled systems. It also provides an analysis of pseudocontinuous versus sampled systems.

Chapter 8 highlights fractional-N frequency synthesis, with a review of delta-sigma modulation fundamentals, quantization theory, noise shaping, and how to achieve modulator stability. It provides a number of different example frequency synthesis architectures.

Chapter 9 reviews linear oscillator theory and provides a sampling of different oscillator configurations, and Chapter 10 investigates clock and data recovery (CDR) techniques for modern digital communications systems.

For anyone serious about designing frequency synthesizers, this will serve as an invaluable reference. Author Jim Crawford is well versed in phase-locked loops, with his earlier text for Artech House, Frequency Synthesizer Design Handbook, published in 1994 serving as an educational reference for many engineers working in frequency synthesis. This latest effort includes a CD-ROM with practical design tools and MATLAB source code. Artech House, 685 Canton St., Norwood, MA 02062; (781) 769-9750, (800) 225-9977, FAX: (781) 769-6334, e-mail: [email protected], Internet:

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