FREQUENCY SYNTHESIZERS are one of the more critical building blocks in wireless communications systems. In quest of a fractional-N digital phase-lock loop (PLL) for frequency synthesizer applications, Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, and Andrea Lacaita of the Dipartmento di Elettronica e Informazione in Milan, Italy fabricated a sigma-delta fractional-N digital PLL. Their design was based on a single time-to-digital converter (TDC) using a standard 65-nm silicon CMOS semiconductor process.
The PLL frequency synthesizer operates from 2.92 to 4.05 GHz with 70-Hz tuning resolution. It exhibits single-sideband phase noise of -102 dBc/Hz offset 50 kHz from the carrier. The device uses a novel architecture, where the sigma-delta quantization noise is subtracted from the output of the TDC, which acts as a phase detector. This approach has previously been used in analog PLLs, but by applying it to this digital version, the subtraction algorithm can be easily implemented. The low jitter of 560 fs at 4.5-mW power reduces to a value of 420 fs RMS when fractional spurious products are not present.
The PLL is designed for use with a 40-MHz reference oscillator. It was characterized for out-of-band fractional spurious products of -53 dBc. The measured phase noise 20 MHz from the carrier is -139 dBc/Hz. The PLL prototype was incorporated in a frequency synthesizer with a two-point modulation scheme, demonstrating a 1.25-Mb/s Gaussian-minimum-shift-keying (GMSK) modulation configuration capable of error-vector-modulation (EVM) level of -31.5 dB. See "A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs RMS Integrated Jitter at 4.5-mW Power," IEEE Journal of Solid-State Circuits, Vol. 46, No. 12, December 2011, p. 2745.