Optimizing PLL Performance Levels Part 2

May 17, 2012
Designing a PLL synthesizer for modern mobile communications systems involves achieving the proper balance among a number of tradeoffs, including spurious levels and frequency switching speed.

Last month, the opening part of this article described how the design of a frequency synthesizer using phase-locked loops (PLLs) can bring high levels of performance, but that certain tradeoffs were necessary, such as between noise levels and switching speed. The choice in different PLL synthesizer parameters ultimately limits the performance levels that will be possible for a given design, and an understanding of those tradeoffs helps to maintain more flexible options when determining the ultimate performance levels for a PLL synthesizer.

In some cases, it may be necessary to push the limits on different performance parameters, such as a PLL frequency synthesizer with low reference spurious levels that also achieves relatively fast locking time. As was shown in Part 1, the loop filter is a critical component in a PLL frequency synthesizer, and can be realized with active or passive filter circuitry, although passive filters are generally preferred for their simplicity, low cost, and good phase-noise performance. Figures 7-10 from Part 1 highlighted various reponses for different cases of loop filters, while Fig. 11 demonstrated the impact of comparison frequency on the lock time for a PLL with a given loop bandwidth (10 kHz). In summary, it was found that when the comparison frequency was much greater (100 times or more) than the loop bandwidth, the rise time of the synthesizer also increases, increasing the lock time.

For further evaluation of the PLL synthesizer, the impact of attenuation on system performance was studied. Every active or passive circuit in a synthesizer will exhibit some attenuation. The attenuation in question for this study is related to the filter pole R3-C3, which must be low enough to provide significant additional reference spurious attenuation and high enough to provide five times the loop bandwidth, so as to not compromise the stability of the loop. After several simulations with different resistor and capacitor values to see the effects on the PLL response, relationships of C3 = C1/10 and R3 = 2R2 for the loop's capacitors and resistors were found to provide an optimal PLL response.

Otherwise, these studies of attenuation confirmed that the choice of high attenuation does not make physical sense. And selecting components for lower attenuation can affect other loop filter parameters, such as causing a null in the time constant T3, which in effect transforms a third-order filter into a second-order filter. Figure 12 shows the effects of attenuation on the frequency responses of the filters used in the PLL frequency design. Figure 13 shows that when the attenuation increases, the loop bandwidth decreases, confirming earlier reports.

A choice of higher attenuation can produce an output signal with enhanced spectral purity, excluding reference spurious products, although it can require longer settling time for the PLL (as shown in Fig. 14 and Fig. 15). Thus, for higher attenuation, the resulting PLL synthesizer output is characterized by higher spectral purity, but with longer lock time (about 12 ms). This is considerably slower than the earlier lock time of about 240 s and not sufficiently fast to meet the requirements of modern mobile communications applications. Finally, Fig. 16 shows that when resistor noise at the output of the PLL's highpass response4 is included in an analysis, the resistor noise has minimal contribution to the synthesizer's output spectrum.

In summary, various tradeoffs were examined in the design of a PLL frequency synthesizer, including between switching time and reference spurious levels. Simulations showed that the settling time is largely determined by the loop bandwidth, comparison frequency, and amount of loop attenuation. The output spectrum obtained using a loop filter with optimal loop bandwidth, 10-dB attenuation, and 200-kHZ comparison frequency presents a noise density of -5.5 dBc/Hz at multiples of the comparison frequency. The switching time for a frequency jump of 25 MHz is about 240 s and the signal-to-noise ratio (SNR) for the design is about 35.67 dB.


  1. G. Singh Patel and S. Sharma, "Comparative Study of PLL, DDS, and DDS-based PLL Synthesis Techniques for Communication System," International Journal of Electronics Engineering, Vol. 2, No. 1, 2010, pp. 35-40.
  2. David Vye,"Performing Transient Analysis on PLL Frequency Synthesizers," Microwave Journal, Vol. 45, No. 1, January 2002, pp. 62-79.
  3. William O. Keese, "An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge-pump PLLs,'' Application Note AN-1001, July 2001, National Semiconductor, Santa Clara, CA, 2006, www.national.com.
  4. S. Kameche, M. Feham, and M. Kameche, "PLL Synthesizer Tunes DCS 1800 Band,'' Microwaves & RF, Vol. 46, No. 6, June 2007, pp. 84-90.
  5. S. Kameche, M. Feham, and M. Kameche, "Simulating and Designing a PLL Frequency Synthesizer for GSM Communications," High Frequency Electronics, Vol. 7, No. 12, December 2008, pp. 36-41.
  6. Jun Lee, "Phase Locked Loop Systems Design for Wireless Infrastructure Applications," Microwave Journal, Vol. 53, No. 5, May 2010, p. 74.
  7. L. Lascari, "Accurate Phase Noise Prediction in PLL Synthesizers," Applied Microwave and Wireless, Vol. 12, No. 2, 2000, pp. 30-38.
  8. D. Banarjee, PLL Performance, Simulation, and Design, 4th ed., National Semiconductor, Santa Clara, CA, 2006, www.national.com.
  9. S. Kameche, M. Feham, and M. Kameche, "Optimizing Lock Time and Reference Spurs in PLL Frequency Synthesizer,'' IEEE International Conference on Electrical and Control Engineering (ICECE) 2011, Yichang, China, September 16-18, 2011.

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