TO ACHIEVE HIGHER DATA RATES in backplane communications, designers tend to improve input/ output (I/O) circuits instead of modifying the board. This approach is easier because of cost and compatibility issues. Yet the I/O usually requires higher power, which may dominate overall power consumption if conventional architectures and circuit structures are used. With novel design approaches, however, it is possible to relax the required power dissipation. For example, power efficiency below 5 mW/Gb/s has been targeted by a recent prototype of a 21-Gb/s backplane transceiver. This device, which was developed by Huaide Wang and Jri Lee at National Taiwan University, incorporates a half-rate topology with purely digital blocks to reduce power consumption.
To keep the structure simple, the receiver employs analog and decision-feedback equalizers in a full-rate structure. The one-tap decisionfeedback equalizer combines the summer and slicer into the flipflop. In doing so, it shortens the feedback path while considerably speeding operation. The transceiver, which is fabricated in 65-nm CMOS, delivers 21-Gb/s data (231 1 PRBS) over a 40-cm FR4 channel while consuming 87 mW from a 1.2-V supply .
A feed-forward equalizer (FFE) was used in the transmitter. This FFE offered speeds above 20 Gb/s. When trying to select the optimal number of taps for such a high-speed FFE, the researchers discovered that the response better fit into the desired response with the more taps that were used. To determine the DFE topology, the tradeoffs of full-rate and half-rate structures were investigated. See "A 21-Gb/s 87-mW Transceiver with FFE/DFE/Analog Equalizer in 65-nm CMOS Technology," IEEE Journal Of Solid-State Circuits, April 2010, p. 909.
