Cryogenic Chip Enhances Satcom System Performance

Jan. 23, 2008
A niobium-based chip in a COTS cryocooler that functions as a high-speed ADC holds great promise for improved microwave communications system performance.

A niobium-based chip in a COTS cryocooler that functions as a high-speed ADC holds great promise for improved microwave communications system performance.

Superconducting circuits and devices offer a great deal of promise in a wide range of industries, including military, commercial, test and measurement, and medical electronic systems. While the technology has been in development for several decades, it has long been limited by the need to maintain temperatures near absolute zero (0 K) in order to achieve the zero-resistance behavior of superconducting circuits. But, by combining its innovative superconducting microelectronic (SME) technology with a small commercial refrigerator, Hypres, Inc. (Elmsford, NY) has developed a prototype microwave receiver front-end solution that has demonstrated improved performance in military satellite-communications (satcom) system testing, without only a fraction of the usual front-end component hardware.

Hypres' efforts in applying its cryogenically cooled electronics to the miniaturization of communications systems is in line with next-generation needs for Defense Satellite Communications System (DSCS) satellite terminals. Most of those terminals employ large parabolic antennas to boost the signal gain to thermal noise (G/T) ratio for relatively low-level received signals. But according to John Deewall, retired head of the Advanced Technology Office of the Product Director, Satellite Communications Systems (PD SCS), part of the Project Manager, Defense Communications and Army Transmission Systems (PM DCATS), which acquires and installs satellite terminals worldwide for the United States military, a current priority is for smaller satcom terminals: "Real estate at many terminal sites around the world is scarce. We've gotten the word to scale down the size of these 18-m 'dinosaurs.'" The satcom terminals rely on traditional superheterodyne-receiver frequency-downconversion methods to translate received X-band signals from the satcom terminal antenna to lower-frequency intermediate-frequency (IF) signals that can be processed and digitized.

This traditional approach employs a series of mixerbased frequency-downconversion stages to shift microwave frequencies to broadband IFs where the modulation information can be captured upon digitization. Military system developers have long sought a true digital receiver in which microwave signals could be directly digitized at the front end, eliminating frequency mixers (and their spurious products) as well as the low-noise amplifiers (LNAs) needed for higher G/T ratios.

The SME-based components and subsystems developed by Hypres represent a potential solution for miniaturizing military satcom and other communications terminals. Hypres recently demonstrated the world's first prototype X-band all-digital receiver (ADR) for PM DCATS under a series of Small Business Innovation Research (SBIR) contracts and PM DCATS support funds. By directly digitizing satcom signals, a great deal of the satcom terminal's analog front-end electronics, such as LNAs, frequency downconverters, cables, and connectors (and their associated signal losses) can be eliminated, clearing the way for the use of small terminal antennas. As a side benefit, use of the superconducting ADR in military satcom terminals can also mean a significant reduction in power consumption. Hypres is currently developing prototype ADR systems configured for specific operating requirements.

The ADR receiver has been made possible by a superconducting chip (Fig. 1) developed by Hypres. Based on the company's niobium substrate material, the chip contains about 11,000 Josephson junctions (JJs) configured to form superconducting Rapid Single Flux Quantum (RSFQ) logic circuits. It is fabricated with the company's 4.5 kA/cm2 SME process. The superconducting benefits of zero resistance and negligible signal losses allow the chip to function as a high-speed analog-to-digital converter (ADC) at noninterleaved clock rates as high as 40 GHz.

Of course, one of the barriers to the use of superconducting circuits in any application has been the need to refrigerate the circuits to achieve performance benefits. Depending upon the type of circuit and the cryogenic temperature required, cooling systems have often involved large dewars of liquid nitrogen or helium subject to relatively rapid dissipation and leakage losses. The Hypres ADR is a dramatic departure from dewar-based designs in that it can achieve its required cryogenic temperatures while packaged in a commercial-off-the-shelf (COTS) two-stage cryocooler (model SRDK- 101D-A11) from Sumitomo Electric.

The compact cryocooler, which employs an air-cooled compressor to achieve the internal gas pressures needed for cooling, features excellent grounding and magnetic shielding with high thermal and electric reliability. The Hypres cryocooler-packaged ADR chip was used in the design of a prototype X-band All-Digital RF(TM) receiver (XADR) for PM-DCATS and the U.S. Army Communications-Electronics Research, Development, and Engineering Center (CERDEC). The chip serves as a bandpass second-order delta-sigma ADC and digital channelizer circuit, both using a common highfrequency clock.

Input signals at X-band are directly converted into an oversampled singlebit data streamdata stream. The channelizer circuit digitally downconverts and filters this digital RF data to produce a pair of digital in-phase (I) and quadrature (Q) words at a reduced (decimated) output clock rate, using a local oscillator at one-fourth the clock frequency. The multiple-bit digital I and Q outputs from the decimation filters are then amplified to about 2 mV using a set of on-chip driver amplifiers. The ADR chip consumes about 4 mW power; the cryocooler used to maintain the chip at 4 K uses about 200 mW heat lift with 1.2 kW prime power from a standard AC supply. Efforts continue to develop a small tactical cooler that will consume less than 500 mW of prime power.

The digital receiver's millivolt-level I and Q output signals, along with the corresponding clock signals, are boosted by a set of custom amplifiers to about 3.3 V. These signals are then acquired using a commercial printed-circuit board (PCB) with field-programmablegate- array (FPGA) devices. In addition to acquiring the digital I and Q data, the interface board permits their transfer to any back-end processor.

To evaluate real-world performance, the X-band ADR (Fig. 2) was tested last year by engineers from Hypres, PM DCATS, and CERDEC at the U.S. Army Joint Satcom Engineering Center (JSEC) in Fort Monmouth, NJ. Tests consisted of transmitting data and video from an AN/GSC- 39 satellite terminal, to an XTAR satellite, and then back down to earth for reception by the same AN/GSC-39 terminal with processing by the XADR. Signals from the XADR were sent to a model 3501-01 modem from L3 Communications (www.l- as part of the testing. CERDEC's Rick Dunnegan, the JSEC lead on the project, noted, "It worked better than expected. The X-band ADR could acquire the signal at the downlink frequency (7.676 GHz) and we were able to digitize, process data directly at X-band, with direct demodulation at X-band. This is a big first step."

Work on the All Digital RF product line is supported by a variety of defense and commercial contracts. ADR development is part of a three-part project at Hypres to create an all-digital transceiver. The other two parts include designing and producing an all-digital transmitter, and then integrating the receiver and transmitter into a complete all-digital transceiver. More information on Hypres' superconducting technology and the company's work on cryogenic ADCs and digital receivers can be found on the firm's website.

Hypres, Inc.,
175 Clearbrook Rd., Elmsford, NY 10523;
(914) 592-1190, FAX: (914) 347-2239,

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