A PHASE-LOCKED LOOP (PLL) -BASED frequency synthesizer requires a certain amount of time for the loop to settle and acquire phase/frequency lock. This settling time, which is determined by the loop characteristics, is inversely proportional to the loop bandwidth. Generally, a PLL's locking time is shortened by widening that loop bandwidth. At Taipei's National Taiwan University, a novel fast-locking technique for PLLs has been developed by Wei-Hao Chiu, Yu-Hsiang Huang, and Tsung-Hsien Lin.
During the locking process, this approach continuously monitors the polarity and magnitude of the phase error at the phase-frequencydetector (PFD) input. To coarsely compensate for the detected phase error, the divide ratio of the frequency divider is changed dynamically. The PLL is able to minimize phase errors through the frequency acquisition process, which reduces the settling time. The locking speed is further enhanced through the use of an auxiliary charge pump. It supplies currents to the loop filter during the fast-locking mode to facilitate a rapid frequency acquisition.
The first step of this method occurs right after the frequency change. At that point, the phase error accumulates quickly because of the large frequency error. Every cycle, the phase error is checked. If it exceeds certain threshold levels, a corresponding phase adjustment is applied to the loop. The complete PLL dissipates 11 mA from a 1.8-V supply. At 5.34 MHz, it typically boasts 114.3 dBc/Hz phase noise offset 1 MHz. The reference spurs at a 10-MHz offset are lower than 70 dBc. See "A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops," IEEE Journal Of Solid-State Circuits, June 2010, p. 1137.
