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Glasgow Scientists Guide Future Nano-Chip Design

GLASGOW, SCOTLANDIn collaboration with colleagues from Edinburgh, Manchester, Southampton, and York universities, scientists at the University of Glasgow have developed technology to help microchip designers create future integrated circuits (ICs). Essentially, the scientists have developed simulation tools that take advantage of grid computing to predict how billions of nano-transistorseach with their own unique and unpredictable atomicscale variationswill perform within a circuit. The simulations will help tackle the problem of statistical variability' within transistors, which is a major obstacle in the continued scaling of complementary-metal-oxide-semiconductor (CMOS) microchips in future nano-scale technology generations. This work is part of a multi-million-Euro Engineering and Physical Sciences Research Council (EPSRC) eScience pilot project called NanoCMOS.

Professor Asen Asenov, the Principal Investigator of NanoCMOS, leads the device modeling team at Glasgow that developed the simulation tools. According to Asenov, "If we are to continue to shrink the size of transistors in order to develop ever-more-powerful circuits, we need fundamentally new approaches to circuit and system design that can take account of the statistical variability."

Asenov and his team have applied gridcomputing technology to tackle the problem in the framework of NanoCMOS. In one week, simulations of huge numbers of microscopically different nano-transistos have been carried out on thousands of microprocessors on networked computer clusters consuming more than 20 years' of CPU time. As a result, the team is able to accurately predict how billions of microscopically different transistors will perform in future computer chips using three-dimensional numerical simulations. This work, which is funded by the EPSRC, is being done in collaboration with leading design houses, chip manufacturers, and software vendors.

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